IP Library Granted Patent US 7,880,653
Granted Patent B2
US 7,880,653 · App. 12/363,201 · Granted Feb 1, 2011

Switched-capacitor circuits, integration systems, and methods of operation thereof

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Quick Facts
Patent No.
US 7,880,653
App. No.
12/363,201
Granted
Feb 1, 2011
Kind
B2
Abstract

Embodiments include integrator systems, switched-capacitor circuits, and methods of their operation. An integrator system comprises a differential amplifier and first and second sampling modules. The first sampling module includes a first capacitor and a first set of switches. The first set of switches changes a connection status between the first capacitor and first and second amplifier input terminals when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and refrains from changing the connection status when the change in the polarity does occur. The second sampling module includes a second capacitor and a second set of switches. The second set of switches changes a connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity does occur, and refrains from changing the connection status when the change in the polarity does not occur.

Claims (70)

1. An integrator system comprising:

a differential amplifier comprising a first differential input that includes a first amplifier input terminal and a second amplifier input terminal;

a first sampling module operatively coupled to the first amplifier input terminal and to the second amplifier input terminal, wherein the first sampling module includes a first capacitor and a first set of switches, wherein the first set of switches is configured to change a connection status between the first capacitor and the first and second amplifier input terminals of the differential amplifier when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and to refrain from changing the connection status between the first capacitor and the first and second amplifier input terminals when the change in the polarity of the differential input signal does occur between the consecutive switching cycles; and

a second sampling module operatively coupled to the first amplifier input terminal and to the second amplifier input terminal, wherein the second sampling module includes a second capacitor and a second set of switches, wherein the second set of switches is configured to change a connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity of the differential input signal does occur, and to refrain from changing the connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity of the differential input signal does not occur.

2. The integrator system of claim 1 , wherein the first sampling module and the second sampling module form portions of a switched-capacitor feedback circuit.

3. The integrator system of claim 1 , further comprising:

an input sampling module operatively coupled to the first amplifier input terminal and to the second amplifier input terminal, and adapted to produce a differential, continuous-time input to the first amplifier input terminal and to the second amplifier input terminal.

4. The integrator system of claim 1 , further comprising:

a switch control module operatively coupled with the first sampling module and with the second sampling module, and adapted to receive the differential input signal, and to provide control signals to the first set of switches and to the second set of switches to cause changes in the connection status between the first capacitor and the first and second amplifier input terminals to occur during certain switching cycles, and to cause changes in the connection status between the second capacitor and the first and second amplifier input terminals to occur during other switching cycles.

5. The integrator system of claim 1 , wherein:

the first set of switches of the first sampling module includes a first switch and a second switch coupled to the first capacitor, wherein the first switch is adapted to connect the first capacitor to the first amplifier input terminal when a first switching signal or when a second switching signal is asserted, and wherein the second switch is adapted to connect the first capacitor to the second amplifier input terminal when a third switching signal or when a fourth switching signal is asserted; and

the second set of switches of the second sampling module include a third switch and a fourth switch coupled to the second capacitor, wherein the third switch is adapted to connect the second capacitor to the first amplifier input terminal when the first switching signal or when the fourth switching signal is asserted, and wherein the fourth switch is adapted to connect the second capacitor to the second amplifier input terminal when the second switching signal or when the third switching signal is asserted.

6. The integrator system of claim 5 , wherein:

the first sampling module further includes a first input and a second input, and the first set of switches further includes a fifth switch and a sixth switch coupled to the first capacitor, wherein the fifth switch is adapted to connect the first capacitor to the first input when a fifth switching signal is asserted, and wherein the sixth switch is adapted to connect the first capacitor to the second input when a sixth switching signal is asserted; and

wherein the second set of switches further includes a seventh switch and an eighth switch coupled to the second capacitor, wherein the seventh switch is adapted to connect the second capacitor to a reference voltage when the fifth switching signal is asserted, and wherein the eighth switch is adapted to connect the second capacitor to the reference voltage when the sixth switching signal is asserted.

7. The integrator system of claim 5 , wherein:

the first sampling module further includes a third capacitor, and the first set of switches further includes a fifth switch and a sixth switch coupled to the third capacitor, wherein the fifth switch is adapted to connect the third capacitor to the first amplifier input terminal when the third switching signal or when the fourth switching signal is asserted, and wherein the sixth switch is adapted to connect the third capacitor to the second amplifier input terminal when the first switching signal or when the second switching signal is asserted; and

wherein the second sampling module further includes a fourth capacitor, and the second set of switches further includes a seventh switch and an eighth switch coupled to the fourth capacitor, wherein the seventh switch is adapted to connect the fourth capacitor to the first amplifier input terminal when the second switching signal or when the third switching signal is asserted, and wherein the eighth switch is adapted to connect the fourth capacitor to the second amplifier input terminal when the first switching signal or when the fourth switching signal is asserted.

8. The integrator system of claim 7 , wherein:

the first sampling module further includes a first input and a second input, and the first set of switches further includes a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch, wherein the ninth switch is adapted to connect the first capacitor to the first input when a fifth switching signal is asserted, and wherein the tenth switch is adapted to connect the first capacitor to the second input when a sixth switching signal is asserted, and wherein the eleventh switch is adapted to connect the third capacitor to the first input when the sixth switching signal is asserted, and wherein the twelfth switch is adapted to connect the third capacitor to the second input when the fifth switching signal is asserted.

9. The integrator system of claim 8 , wherein:

the second set of switches further includes a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch, wherein the thirteenth switch is adapted to connect the second capacitor to a reference voltage when the fifth switching signal is asserted, and wherein the fourteenth switch is adapted to connect the second capacitor to the reference voltage when the sixth switching signal is asserted, and wherein the fifteenth switch is adapted to connect the fourth capacitor to the reference voltage when the sixth switching signal is asserted, and wherein the sixteenth switch is adapted to connect the fourth capacitor to the reference voltage when the fifth switching signal is asserted.

10. The integrator system of claim 9 , further comprising:

a switch control module operatively coupled with the first sampling module and with the second sampling module, and adapted to provide the first switching signal, the second switching signal, the third switching signal, the fourth switching signal, the fifth switching signal, and the sixth switching signal.

11. The integrator system of claim 8 , wherein the second capacitor is connected to a reference voltage, and wherein the fourth capacitor is connected to a reference voltage.

12. A switched-capacitor circuit comprising:

a first output node;

a second output node;

a first sampling module coupled to the first and second output nodes, wherein the first sampling module includes a first capacitor, a first switch, and a second switch, wherein the first switch is adapted to connect the first capacitor to the first output node when a first switching signal or when a second switching signal is asserted, and wherein the second switch is adapted to connect the first capacitor to the second output node when a third switching signal or when a fourth switching signal is asserted, and wherein the first switch and the second switch are configured to change a connection status between the first capacitor and the first and second output nodes when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and to refrain from changing the connection status between the first capacitor and the first and second output nodes when the change in the polarity of the differential input signal does occur between the consecutive switching cycles; and

a second sampling module coupled to the first and second output nodes, wherein the second sampling module includes a second capacitor, a third switch, and a fourth switch, wherein the third switch is adapted to connect the second capacitor to the first output node when the first switching signal or when the fourth switching signal is asserted, and wherein the fourth switch is adapted to connect the second capacitor to the second output node when the second switching signal or when the third switching signal is asserted, wherein the third switch and the fourth switch are configured to change a connection status between the second capacitor and the first and second output nodes when the change in the polarity of the differential input signal does occur, and to refrain from changing the connection status between the second capacitor and the first and second output nodes when the change in the polarity of the differential input signal does not occur.

13. A switched-capacitor circuit comprising:

a first output node;

a second output node;

a first sampling module coupled to the first and second output nodes, wherein the first sampling module includes a first capacitor, a first switch, and a second switch, wherein the first switch is adapted to connect the first capacitor to the first output node when a first switching signal or when a second switching signal is asserted, and wherein the second switch is adapted to connect the first capacitor to the second output node when a third switching signal or when a fourth switching signal is asserted; and

a second sampling module coupled to the first and second output nodes, wherein the second sampling module includes a second capacitor, a third switch, and a fourth switch, wherein the third switch is adapted to connect the second capacitor to the first output node when the first switching signal or when the fourth switching signal is asserted, and wherein the fourth switch is adapted to connect the second capacitor to the second output node when the second switching signal or when the third switching signal is asserted, wherein

the first sampling module further includes a first input, a second input, a fifth switch, and a sixth switch, wherein the fifth switch is adapted to connect the first capacitor to the first input when a fifth switching signal is asserted, and wherein the sixth switch is adapted to connect the first capacitor to the second input when a sixth switching signal is asserted; and

wherein the second sampling module further includes a seventh switch and an eighth switch, wherein the seventh switch is adapted to connect the second capacitor to a reference voltage when the fifth switching signal is asserted, and wherein the eighth switch is adapted to connect the second capacitor to the reference voltage when the sixth switching signal is asserted.

14. A switched-capacitor circuit comprising:

a first output node;

a second output node;

a first sampling module coupled to the first and second output nodes, wherein the first sampling module includes a first capacitor, a first switch, and a second switch, wherein the first switch is adapted to connect the first capacitor to the first output node when a first switching signal or when a second switching signal is asserted, and wherein the second switch is adapted to connect the first capacitor to the second output node when a third switching signal or when a fourth switching signal is asserted; and

a second sampling module coupled to the first and second output nodes, wherein the second sampling module includes a second capacitor, a third switch, and a fourth switch, wherein the third switch is adapted to connect the second capacitor to the first output node when the first switching signal or when the fourth switching signal is asserted, and wherein the fourth switch is adapted to connect the second capacitor to the second output node when the second switching signal or when the third switching signal is asserted, wherein

the first sampling module further includes a third capacitor, and the first set of switches further includes a fifth switch and a sixth switch coupled to the third capacitor, wherein the fifth switch is adapted to connect the third capacitor to the first output node when the third switching signal or when the fourth switching signal is asserted, and wherein the sixth switch is adapted to connect the third capacitor to the second output node when the first switching signal or when the second switching signal is asserted; and

wherein the second sampling module further includes a fourth capacitor, and the second set of switches further includes a seventh switch and an eighth switch coupled to the fourth capacitor, wherein the seventh switch is adapted to connect the fourth capacitor to the first output node when the second switching signal or when the third switching signal is asserted, and wherein the eighth switch is adapted to connect the fourth capacitor to the second output node when the first switching signal or when the fourth switching signal is asserted.

15. The circuit of claim 14 , wherein:

the first sampling module further includes a first input and a second input, and the first set of switches further includes a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch, wherein the ninth switch is adapted to connect the first capacitor to the first input when a fifth switching signal is asserted, and wherein the tenth switch is adapted to connect the first capacitor to the second input when a sixth switching signal is asserted, and wherein the eleventh switch is adapted to connect the third capacitor to the first input when the sixth switching signal is asserted, and wherein the twelfth switch is adapted to connect the third capacitor to the second input when the fifth switching signal is asserted.

16. The circuit of claim 15 , wherein:

the second set of switches further includes a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch, wherein the thirteenth switch is adapted to connect the second capacitor to a reference voltage when the fifth switching signal is asserted, and wherein the fourteenth switch is adapted to connect the second capacitor to the reference voltage when the sixth switching signal is asserted, and wherein the fifteenth switch is adapted to connect the fourth capacitor to the reference voltage when the sixth switching signal is asserted, and wherein the sixteenth switch is adapted to connect the fourth capacitor to the reference voltage when the fifth switching signal is asserted.

17. The integrator system of claim 14 , wherein the second capacitor is connected to a reference voltage, and wherein the fourth capacitor is connected to a reference voltage.

18. A method performed in an integration system that includes a switched-capacitor feedback circuit coupled to a differential input of a differential amplifier, the method comprising:

during each of a plurality of switching cycles, monitoring a first differential signal to determine a polarity of the first differential signal, the polarity of the first differential signal capable of being positive or negative;

in response to the polarity of the first differential signal changing between positive and negative, refraining from causing a first sampling module of the switched-capacitor feedback circuit to change a connection status between a first capacitor of the first sampling module and the differential input of the differential amplifier, and causing a second sampling module of the switched-capacitor feedback circuit to change a connection status between a second capacitor of the second sampling module and the differential input of the differential amplifier; and

in response to the polarity of the first differential signal remaining positive or negative, and not changing between consecutive switching cycles, causing the first sampling module to change the connection status between the first capacitor and the differential input, and refraining from causing the second sampling module to change the connection status between the second capacitor and the differential input.

19. The method of claim 18 , wherein the first sampling module includes a first switch and a second switch coupled to the first capacitor, and wherein causing the first sampling module to change the connection status comprises:

providing a switching signal adapted to cause the first switch to change its state of being opened or closed; and

providing a switching signal adapted to cause the second switch to change its state of being opened or closed.

20. The method of claim 19 , wherein the second sampling module includes a third switch and a fourth switch, and wherein causing the second sampling module to change the connection status comprises:

providing a switching signal adapted to cause the third switch to change its state of being opened or closed; and

providing a switching signal adapted to cause the fourth switch to change its state of being opened or closed.

21. The method of claim 20 , wherein the first sampling module includes a first input, a second input, a fifth switch and a sixth switch, and the method further comprises:

at certain times, providing a switching signal adapted to cause the fifth switch to close, thus connecting the first input with the first capacitor; and

at other times, providing a switching signal adapted to cause the sixth switch to close, thus connecting the second input with the first capacitor.

22. The method of claim 21 , wherein the second sampling module includes a connection to a reference voltage, a seventh switch, and an eighth switch, and the method further comprises:

at certain times, providing a switching signal adapted to cause the seventh switch to close, thus connecting the reference voltage with the second capacitor; and

at other times, providing a switching signal adapted to cause the eighth eight switch to close, thus connecting the reference voltage with the second capacitor.

23. The method of claim 22 , wherein the differential amplifier further includes a differential output, and the method further comprises:

integrating a difference between signals present at the differential input to produce a second differential signal at the differential output.

24. The method of claim 23 , further comprising:

summing the second differential signal with a third, data-bearing differential signal to produce a modified, data-bearing differential signal; and

integrating and quantizing the modified, data-bearing differential signal to produce the first differential signal.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
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To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: FREESCALE SEMICONDUCTOR INC.
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From: FREESCALE SEMICONDUCTOR INC.
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To: NXP B.V.
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RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
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To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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