Barrier for use in 3-D integration of circuits
View Patent ↗A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.
1. A method for forming a semiconductor device, comprising:
providing a first integrated circuit having a landing feature;
attaching a second integrated circuit to the first integrated circuit, the second integrated circuit having an inter-circuit trace, the inter-circuit trace having an inter-circuit trace opening;
forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening to the landing pad;
forming a selective barrier on exposed portions of the inter-circuit trace in the opening; and
filling the opening with a conductive fill material, wherein the conductive fill material electrically connects the inter-circuit trace and the landing feature.
2. The method of claim 1 , wherein selective barrier comprises a material selected from a group consisting of cobalt and nickel.
3. The method of claim 1 , wherein the selective barrier comprises cobalt.
4. The method of clam 3 , wherein the selective barrier comprises tungsten.
5. The method of claim 1 , wherein the selective barrier is formed only on the exposed portions of the inter-circuit trace in the opening.
6. The method of claim 1 , wherein the landing pad comprises a conductive barrier layer comprising a material selected from a group consisting of cobalt and nickel.
7. The method of claim 1 , wherein attaching the second integrated circuit to the first integrated circuit comprises attaching the second integrated circuit to the first integrated circuit using at least one bonding layer between the first and second integrated circuit.
8. The method of claim 7 , wherein forming the opening comprises:
forming the opening extending through the second integrated circuit and the inter-circuit trace opening to the at least one bonding layer; and
extending the opening through the at least one bonding layer to the landing feature, wherein the landing feature comprises at least one of a landing pad and a metal trace.
9. The method of claim 1 , wherein the inter-circuit trace comprises an inter-circuit trace barrier layer, and wherein prior to forming the selective barrier, the method further comprises treating exposed portions of the inter-circuit trace barrier layer.
10. The method of claim 1 further comprising forming a liner layer in the opening, prior to filling the opening with the conductive fill material.
11. The method of claim 1 , wherein the inter-circuit trace comprises copper.
12. A method for forming a semiconductor device, comprising:
providing a first integrated circuit having a landing feature;
attaching a second integrated circuit to the first integrated circuit using at least one bonding layer, the second integrated circuit having an inter-circuit trace, the inter-circuit trace having an inter-circuit trace opening;
forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening;
forming a selective barrier on exposed portions of the inter-circuit trace in the opening, the selective barrier comprising at least one material selected from a group consisting of cobalt and nickel;
extending the opening through the at least one bonding layer to the landing feature; and
after extending the opening, filling the opening with a conductive fill material, wherein the conductive fill material electrically connects the inter-circuit trace and the landing feature.
13. The method of claim 12 , wherein attaching the second integrated circuit to the first integrated circuit using the at least one bonding layer comprises:
attaching a first bonding layer formed on the first integrated circuit and a second bonding layer formed on the second integrated circuit.
14. The method of claim 12 , wherein the inter-circuit trace comprises an inter-circuit trace barrier layer and wherein the exposed portions of the inter-circuit trace comprise at least a portion of the inter-circuit trace barrier layer, and wherein prior to forming the selective barrier, the method further comprises treating the at least a portion of the inter-circuit trace barrier layer.
15. The method of claim 12 , wherein the at least one bonding layer comprises an etch stop layer, and wherein forming the opening through the second integrated circuit is performed such that the opening extends to the etch stop layer.
16. The method of claim 12 further comprising forming a liner layer in the opening, after extending the opening and prior to filling the opening.
17. The method of claim 12 , wherein the landing feature comprises a conductive barrier layer comprising a material selected from a group consisting of cobalt and nickel, and wherein extending the opening through the at least one bonding layer to the landing feature is performed such that the opening exposes the conductive barrier layer of the landing feature.