IP Library Granted Patent US 7,378,197
Granted Patent B2
US 7,378,197 · App. 11/267,983 · Granted May 27, 2008

Method of patterning photoresist on a wafer using a reflective mask with a multi-layer ARC

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Quick Facts
Patent No.
US 7,378,197
App. No.
11/267,983
Granted
May 27, 2008
Kind
B2
Abstract

A patterned reflective semiconductor mask uses a multiple layer ARC overlying an absorber stack that overlies a reflective substrate. The absorber stack has more than one layer and an upper layer of the absorber stack has a predetermined metal. The multiple layer ARC overlying the upper layer of the absorber stack has layers of nitrogen, oxygen and nitrogen combined with the predetermined metal of the upper layer of the absorber stack. The oxygen layer in the ARC has less metallic properties than the nitrogen layers therein. In one form, an overlying dielectric layer is positioned on the multiple layer ARC to increase light interference. The ARC provides wide bandwidth inspection contrast for extreme ultra-violet (EUV) reticles.

Claims (30)

1. A semiconductor mask comprising:

a substrate;

a reflecting layer overlying the substrate for reflecting light from the semiconductor mask;

an absorber stack selectively formed overlying the reflecting layer, the absorber stack having a plurality of layers, an upper layer of the absorber stack that is opposite the reflecting layer comprises a predetermined metal; and

a multiple layer anti-reflective coating overlying the upper layer of the absorber stack, the multiple layer anti-reflective coating comprising adjoining layers that respectively have nitrogen, oxygen and nitrogen combined with the predetermined metal of the upper layer of the absorber stack.

2. The semiconductor mask of claim 1 wherein the multiple layer anti-reflective coating further comprises:

an overlying dielectric layer adjacent the multiple layer anti-reflective coating comprising a predetermined material, the overlying dielectric layer providing additional destructive interference of light for a wider bandwidth of inspection wavelengths.

3. The semiconductor mask of claim 2 wherein the predetermined dielectric material comprises one of silicon oxygen nitride, silicon nitride or silicon oxide.

4. The semiconductor mask of claim 1 wherein the predetermined metal further comprises one of tantalum, chromium, tungsten, tantalum silicide, tantalum boride and oxides and nitrides thereof.

5. The semiconductor mask of claim 1 wherein the multiple layer anti-reflective coating comprising adjoining layers respectively having nitrogen, oxygen and nitrogen respectively comprise tantalum silicon nitride, tantalum silicon oxide and tantalum silicon nitride.

6. The semiconductor mask of claim 1 wherein the multiple layer anti-reflective coating further comprises a concentration of nitrogen and oxygen that is greater than any nitrogen or oxygen in the predetermined metal of the upper layer of the absorber stack.

7. The semiconductor mask of claim 1 wherein a layer of the adjoining layers having oxygen has less metallic properties than remaining layers of the adjoining layers.

8. The semiconductor mask of claim 1 wherein an inspection contrast of the semiconductor mask is greater than seventy percent (70%) at multiple inspection wavelengths.

9. The semiconductor mask of claim 1 wherein the reflectivity of the multiple layer anti-reflective coating is less than ten percent (10%) at multiple inspection wavelengths.

10. A method of providing a semiconductor mask comprising:

providing a substrate;

forming a reflecting layer overlying the substrate for reflecting light from the semiconductor mask;

forming an absorber stack selectively formed overlying the reflecting layer, the absorber stack having a plurality of layers, an upper layer of the absorber stack that is opposite the reflecting layer comprises a predetermined metal; and

forming a multiple layer anti-reflective coating overlying the upper layer of the absorber stack, the multiple layer anti-reflective coating comprising adjoining layers that respectively have nitrogen, oxygen and nitrogen combined with the predetermined metal of the upper layer of the absorber stack.

11. The method of claim 10 further comprising:

forming an overlying dielectric layer comprising a predetermined material, the overlying dielectric layer providing additional destructive interference of light for a wider bandwidth of inspection wavelengths.

12. The method of claim 11 further comprising forming the predetermined material from one of silicon oxygen nitride, silicon nitride or silicon oxide.

13. The method of claim 10 further comprising forming the predetermined metal from one of tantalum, chromium, tungsten, tantalum silicide, tantalum boride and oxides and nitrides thereof.

14. The method of claim 10 further comprising forming the multiple layer anti-reflective coating comprising adjoining layers respectively from tantalum silicon nitride, tantalum silicon oxide and tantalum silicon nitride.

15. The method of claim 10 further comprising forming the multiple layer anti-reflective coating from a concentration of nitrogen and oxygen that is greater than any nitrogen or oxygen in the predetermined metal of the upper layer of the absorber stack.

16. The method of claim 10 further comprising forming the multiple layer anti-reflective coating from a layer of oxygen within the adjoining layers, the layer of oxygen having less metallic properties than the remaining adjoining layers.

17. The method of claim 10 further comprising forming the multiple layer anti-reflective coating having physical characteristics so that an inspection contrast of the semiconductor mask is greater than seventy percent (70%) at multiple inspection wavelengths.

18. The method of claim 10 further comprising forming the mask with materials in the multiple layer anti-reflective coating having physical properties so that a reflectivity of the multiple layer anti-reflective coating is less than ten percent (10%) at multiple inspection wavelengths.

19. The method of claim 10 further comprising:

forming a semiconductor pattern in both the predetermined metal of the upper layer of the absorber stack and the multiple layer anti-reflective coating with a same process etch step.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0719 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →