Standby control circuit and method
View Patent ↗A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.
1. A standby control circuit for an integrated circuit module having a primary clock circuit for providing a primary clock signal which is active in a normal operating mode of the integrated circuit module and inactive in a reduced power mode of the integrated circuit module, and a secondary clock circuit for providing a secondary clock signal independently of the mode of the integrated circuit module, the standby control circuit comprising:
a first control circuit responsive, in the normal operating mode, to an asynchronous standby signal indicating a standby mode entry event to output, synchronous with the primary clock signal, a standby mode signal indicating a standby operating mode of the integrated circuit module; and
a second control circuit responsive, in the reduced power mode, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with the secondary clock signal to indicate the standby operating mode, and
wherein the first control circuit includes a first synchronizer circuit comprising at least two edge triggered registers that receive the primary clock signal as a clock input,
the first synchronizer circuit has an input that receives the asynchronous standby signal, and an output for providing the standby mode signal synchronous with the primary clock signal, and wherein the first synchronizer circuit provides the standby mode signal within a first predetermined delay of the asynchronous standby signal.
2. A standby control circuit according to claim 1 , wherein the first synchronizer circuit comprises oppositely edge triggered registers.
3. A standby control circuit according to claim 2 , wherein the output of the first synchronizer circuit is provided by a negatively edge triggered register.
4. A standby control circuit according to claim 2 , wherein the first predetermined delay is less than a decay time associated with removal of a primary supply of power, being the decay time for the output voltage of the primary supply of power to decrease from a minimum voltage representing a logic 1 state value to a maximum voltage value representing a logic 0 state.
5. A standby control circuit according to claim 1 , wherein each register of the first synchronizer circuit includes an asynchronous input coupled to an output of the second control circuit to permit the second control circuit to control, in the reduced power mode, the first control circuit to output the standby mode signal.
6. A standby control circuit according to claim 1 , wherein the second control circuit includes at least one additional synchronizer circuit, each additional synchronizer circuit comprising at least two edge triggered registers receiving the secondary clock signal as a clock input, each additional synchronizer circuit having an input for receiving the asynchronous standby signal, and an output for providing, responsive to the asynchronous standby signal indicating the standby mode entry event, an output signal synchronous with the secondary clock signal, the additional synchronizer circuits being arranged so that one of the additional synchronizer circuits provides its output within a second predetermined delay of the asynchronous standby signal indicating the standby mode entry event.
7. A standby control circuit according to claim 6 , wherein the second predetermined delay is greater than the first predetermined delay.
8. A standby control circuit according to claim 7 , wherein the second predetermined delay is greater than the first predetermined delay by a time period equivalent to no less than two clock cycles of the primary clock signal.
9. A standby control circuit according to claim 7 , wherein the second predetermined delay is greater than the first predetermined delay by a time period which provides the first control circuit with sufficient time to respond to the asynchronous standby signal indicating a standby mode entry event if the primary clock was active.
10. A standby control circuit according to claim 7 , wherein the second predetermined delay is about 32 μS.
11. A standby control circuit according to claim 1 , further including a logic circuit responsive, in the standby mode, to the asynchronous standby signal to control the first control circuit to delay a further control of the standby mode signal, the further control for indicating the normal operating mode.
12. A standby control circuit according to claim 1 , wherein in the normal operating mode the first control circuit outputs the standby mode signal within a first predetermined delay of the asynchronous standby signal indicating the standby mode entry event, and wherein in the reduced power mode the second control circuit controls the first control circuit to output the standby mode signal within a second predetermined delay of the asynchronous standby signal indicating the standby mode entry event, and wherein the second predetermined delay is greater than the first predetermined delay.
13. An integrated circuit module, comprising:
a first input for receiving a first output voltage supply from a primary supply of power;
a second input for receiving a second output voltage supply from a secondary supply of power;
a detector for receiving the first input and generating an asynchronous standby signal in response to the first output voltage supply being removed from the integrated circuit module, the asynchronous standby signal for indicating a standby mode entry event;
a primary clock circuit for providing a primary clock signal which is active in a normal operating mode of the integrated circuit module and inactive in a reduced power mode of the integrated circuit module;
a secondary clock circuit for providing a secondary clock signal independently of the mode of the integrated circuit module; and
a standby control circuit comprising:
a first control circuit responsive, in the normal operating mode, to the asynchronous standby to output, synchronous with the primary clock signal, a standby mode signal indicating a standby operating mode of the integrated circuit module; and
a second control circuit responsive, in the reduced power mode, to the asynchronous standby signal to control the first control circuit to output the standby mode signal synchronous with the secondary clock signal to indicate the standby operating mode.
14. An integrated circuit module according to claim 13 , wherein the first control circuit includes a first synchronizer circuit comprising at least two edge triggered registers receiving the primary clock signal as a clock input,
the first synchronizer circuit having an input for receiving the asynchronous standby signal, and an output for providing the standby mode signal synchronous with the primary clock signal,
wherein the first synchronizer provides the standby mode signal within a first predetermined delay of the asynchronous standby signal indicating the standby mode entry event.
15. An integrated circuit module according to claim 14 , wherein the first synchronizer circuit comprises oppositely edge triggered registers.
16. An integrated circuit module according to claim 15 , wherein the output of the first synchronizer circuit is provided by a negatively edge triggered register.
17. An integrated circuit module according to claim 13 , wherein in the normal operating mode the first control circuit outputs standby mode signal within a first predetermined delay of the asynchronous standby signal indicating the standby mode entry event, and wherein in the reduced power mode the second control circuit controls the first control circuit to output the standby mode signal within a second predetermined delay of the asynchronous standby signal indicating the standby mode entry event, and wherein the second predetermined delay is greater than the first predetermined delay.