System for integrated data integrity verification and method thereof
View Patent ↗In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at least a subset of the first plurality of values are accumulated in one or more accumulators. The one or more accumulators are accessed to obtain a first accumulated value and the first accumulated value is compared with a first expected accumulated value. In accordance with a second technique, a first plurality of load operations are performed at a processor to access data values stored in a first sequence of fields of a memory. The data values are accumulated in one or more accumulators of the processor to generate a first accumulated value and it is determined whether the memory has been corrupted based on a comparison of the first accumulated value to a first expected accumulation value.
1. A method comprising:
receiving, at a processor, a plurality of values from a memory;
for each value of a subset of the plurality of values:
determining a characteristic associated with the value;
accumulating a most significant bit portion of the value in a first accumulator and accumulating a least significant bit portion of the value in a second accumulator responsive to determining the characteristic is compatible with a permitted accumulation characteristic;
avoiding accumulation of the most significant bit portion of the value in the first accumulator and avoiding accumulation of the least significant bit portion of the value in the second accumulator responsive to determining the characteristic is incompatible with the permitted accumulation characteristic; and
accessing at least one of the first and the second accumulator to obtain an accumulated value; and
comparing the accumulated value with an expected accumulated value.
2. The method of claim 1 , wherein the at least one of the first accumulator and the second accumulator includes a multiple-input signature register (MISR).
3. The method of claim 1 , wherein the characteristic is an address value and the permitted accumulation characteristic is an address range.
4. The method of claim 1 , wherein the characteristic is a data transfer type and the permitted accumulation characteristic is one or more permitted data transfer types.
5. The method of claim 1 , wherein accessing at least one of the first accumulator and the second accumulator comprises:
reading the accumulated value from one or more registers associated with the at least one of the first accumulator and the second accumulator.
6. The method of claim 1 , further comprising:
initializing at least one of the first accumulator and the second accumulator.
7. The method of claim 6 , wherein initializing at least one of the first accumulator and the second accumulator comprises:
writing an initialization value to one or more registers associated with at least one of the first accumulator or the second accumulator.
8. The method of claim 1 , further comprising:
identifying at least the subset of the plurality of values as invalid when the accumulated value is not equal to the expected accumulated value.
9. A method comprising:
performing a plurality of load operations at a processor to access data values stored in a sequence of fields of a memory;
accumulating a most significant bit portion of each data value in a first accumulator and accumulating a least significant bit portion of each data value in second accumulator for each data value having a characteristic compatible with a permitted accumulation characteristic to generate an accumulated value; and
determining whether the memory has been corrupted based on a comparison of the accumulated value to an expected accumulation value.
10. The method of claim 9 , wherein the data values are representative of at least one of: instruction data, operation data or constants.
11. The method of claim 9 , wherein comparing the accumulated value to the expected accumulated value comprises obtaining the accumulated value from one or more registers of the processor associated with the at least one of the first accumulator and the second accumulator.
12. A processor comprising:
a bus interface unit operable to couple to one or more busses connected to a memory;
a first accumulator;
a second accumulator;
an execution unit operable to perform one or more data transfer operations between the processor and the memory via the one or more busses; and
a control module operable to:
for each value of at least a subset of one or more values received from the bus interface unit;
determine a characteristic associated with the value; and
provide a most significant bit portion of the value to the first accumulator and a least significant bit portion of the value to the second accumulator for accumulation responsive to the characteristic being compatible with a permitted accumulation characteristic.
13. The processor of claim 12 , wherein the first accumulator includes a first multiple input signature register (MISR) and the second accumulator includes a second MISR.
14. The processor of claim 12 , further comprising:
a first set of one or more registers operable to receive a first initialization value for initializing the at least the first accumulator;
a second set of one or more registers operable to receive an accumulated value from at least the first accumulator;
a third set of one or more registers operable to receive a second initialization value for initializing the at least the second accumulator; and
a fourth set of one or more registers operable to receive an accumulated value from at least the second accumulator.
15. The processor of claim 14 , wherein the execution unit is operable to obtain an accumulated value via the second set of one or more registers and the fourth set of one or more registers.
16. The processor of claim 14 , wherein the execution unit is further operable to initialize the first accumulator by writing the first initialization value to the first set of one or more registers and initialize the second accumulator by writing the second initialization value to the third set of one or more registers.
17. The processor of claim 12 , wherein the characteristic is an address value and the permitted accumulation characteristic is an address range.
18. The processor of claim 12 , wherein the characteristic is a data transfer type and the permitted accumulation characteristic is one or more permitted data transfer types.
19. A method comprising:
when in a first mode:
initializing an accumulator of a processor with a seed value;
accumulating a first set of one or more values at the accumulator; and
utilizing a first resulting accumulated value as a pseudo-random number by one or more programs of the processor; and
when in a second mode:
accumulating a second set of one or more values at the accumulator, the one or more values of the second set obtained from a predetermined sequence of data transfers between the processor and a memory; and
determining an integrity of the memory based on a comparison of a second resulting accumulated value with an expected accumulated value.
20. The method of claim 19 , wherein the one or more values of the first set are obtained from data transfers between the processor and a memory.
21. The method of claim 19 , wherein the one or more values of the first set are obtained from executing register movement instructions to transfer data values from a processor general purpose register to the accumulator within the processor.
22. The method of claim 19 , wherein accumulating the second set of one or more values at the accumulator comprises:
determining a characteristic associated with a select value of the second set of one or more values;
accumulating the select value when the characteristic is compatible with a permitted accumulation characteristic; and
avoiding accumulation of the select value when the characteristic is incompatible with the permitted accumulation characteristic.
23. The method of claim 22 , wherein the characteristic is an address value and the permitted accumulation characteristic is an address range.
24. The method of claim 22 , wherein the characteristic is a data transfer type and the permitted accumulation characteristic is one or more permitted data transfer types.
25. The method of claim 19 , further comprising:
initializing the accumulator.
26. The method of claim 25 , wherein initializing the accumulator comprises:
writing an initialization value to one or more registers associated with the accumulator.
27. The method of claim 19 , further comprising:
identifying at least the subset of the second set of one or more values as invalid when the second resulting accumulated value is not equal to the expected accumulated value.
28. A processor comprising:
a bus interface unit operable to couple to one or more busses connected to a memory;
an execution unit operable to perform one or more data transfer operations between the processor and the memory via the one or more busses.
an accumulator operable to:
in a first mode:
accumulate a first set of one or more values obtained from one or more data transfer operations between the processor and the memory; and
provide a first resulting accumulated value as a pseudo-random number for use by one or more programs executed at the processor; and
in a second mode:
accumulate a second set of one or more values obtained from a predetermined sequence of data transfers operations between the processor and the memory; and
determine an integrity of the memory based on a comparison of a second resulting accumulated value with an expected accumulated value.
29. The processor of claim 28 , wherein the accumulator includes a first multiple input signature register (MISR).
30. The processor of claim 28 , further comprising:
a first set of one or more registers operable to receive an initialization value for initializing the accumulator; and
a second set of one or more registers operable to receive an accumulated value from the accumulator.
31. The processor of claim 30 , wherein the execution unit is operable to obtain an accumulated value via the second set of one or more registers.
32. The processor of claim 30 , wherein the execution unit is further operable to initialize the accumulator by writing the initialization value to the first set of one or more registers.