Methods and apparatus for a stepped-drift MOSFET
View Patent ↗A power metal-oxide-semiconductor field effect transistor (MOSFET)( 100 ) incorporates a stepped drift region including a shallow trench insulator (STI)( 112 ) partially overlapped by the gate ( 114 ) and which extends a portion of the distance to a drain region ( 122 ). A silicide block extends from and partially overlaps STI ( 112 ) and drain region ( 122 ). The STI ( 112 ) has a width that is approximately 50% to 75% of the drift region.
1. A metal-oxide semiconductor field effect transistor (MOSFET) comprising:
a drain region having a first conductivity type;
a source region having the first conductivity type;
a gate provided between the drain region and the source region; and
a shallow-trench isolation (STI) region partially overlapped by the gate and extending partially to the drain region;
a silicide block layer extending between and contacting the gate, the STI, and the drain regions.
2. The MOSFET of claim 1 , wherein:
the STI has a first edge and a second edge, wherein the first edge and the second edge of the STI is separated by a distance d 1 ;
the drain region has a first edge, wherein the first edge of the drain region and the first edge of the STI are separated by a distance d 2 ;
the ratio d 1 /d 2 is less than about 0.75.
3. The MOSFET of claim 2 , wherein the ratio d 1 /d 2 is greater than about 0.50.
4. The MOSFET of claim 2 , further comprising a buried layer having the first conductivity type, wherein the buried layer is coupled to the drain or source region.
5. The MOSFET of claim 2 , wherein the drain region is formed in a semiconductor layer having the first conductivity type and having a dopant concentration that is less than a dopant concentration of the drain region.
6. A stepped drift structure for use in connection with a MOSFET device having a drain diffusion and a gate, said stepped drift structure comprising:
a shallow-trench isolation (STI) region partially overlapped by the gate and extending a portion of a distance to the drain diffusion;
a silicide block layer extending between and contacting the gate, the STI, and the drain diffusion.
7. The stepped drift structure of claim 6 , wherein the STI extends less than approximately 75% of the distance to the drain diffusion.
8. The stepped drift structure of claim 7 , wherein the STI extends greater than approximately 50% of the distance to the drain diffusion.
9. The stepped drift structure of claim 7 , wherein the silicide block extends to and contacts the gate.
10. A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) comprising:
forming a drain region having a first conductivity type;
forming a source region having the first conductivity type;
forming a shallow-trench isolation (STI) region between the drain region and the source region, wherein the STI extends partially to the drain region;
forming a gate between the drain region and the source region, wherein the gate partially overlaps the STI; and
forming a silicide block layer extending between and contacting the gate, the STI, and the drain regions.
11. The method of claim 10 , wherein:
the STI is formed such that it has a first edge and a second edge separated by a distance d 1 ;
the drain region is formed such that it has a first edge, separated from the first edge of the STI by a distance d 2 , wherein the ratio d 1 /d 2 is less than about 0.75.
12. The method of claim 11 , wherein the ratio d 1 /d 2 is greater than about 0.50.
13. The method of claim 10 , further comprising forming a buried layer having the first conductivity type, wherein the buried layer is coupled to the drain region.
14. The method of claim 10 , wherein the drain region is formed in a semiconductor layer having the first conductivity type and having a dopant concentration that is less than a dopant concentration of the drain region.
15. The method of claim 10 , wherein the first conductivity type is N-type.
16. The method of claim 10 , wherein the first conductivity type is P-type.