Method for manufacturing a passive integrated matching network for power amplifiers
View Patent ↗An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.
1. An impedance matching network integrated on a first die and coupled to a second die, the first and second dies being mounted on a conductive back plate, the impedance matching network comprising:
a first inductor bridging between the first and second dies;
a second inductor coupled to the first inductor and disposed on the first die; and
a metal-insulator-metal capacitor disposed on the first die, and having a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate.
2. The impedance matching network according to claim 1 , wherein the first die comprises GaAs.
3. The impedance matching network according to claim 1 , wherein the first die is between about 75 and about 200 μm in thickness.
4. The impedance matching network according to claim 1 , wherein the first inductor comprises a plurality of bond wires, and the second inductor comprises a plurality of metal strips.
5. The impedance matching network according to claim 4 , wherein each of the metal strips is more than 8 μm in thickness, and more than 40 μm in width.
6. The impedance matching network according to claim 4 , wherein each of the bond wires is between about 10 mils and about 30 mils in height.
7. The impedance matching network according to claim 1 , wherein the second die is selected from the group consisting of an LDMOS and a III-V compound semiconductor die.
8. The impedance matching network according to claim 1 , wherein the second die comprises a power amplification circuit.
9. The impedance matching network according to claim 1 , wherein the first die has a via hole formed therethrough between the conductive back plate and the metal-insulator-metal capacitor second metal layer, the via hole filled with an interconnect metal.
10. The impedance matching network according to claim 1 , wherein the second inductor is coupled to the metal-insulator-metal capacitor first metal layer using a third metal, and wherein the second inductor, the metal-insulator-metal capacitor first and second metal layers, and the third metal are formed from the same materials.
11. A power amplifier for a base station that amplifies and transmits remote signals, the power amplifier comprising:
a conductive plate;
a first die comprising a power amplification circuit and mounted on the conductive plate;
a second die mounted on the conductive plate and having an impedance matching network integrated thereon and coupled to the first die, the impedance matching network comprising:
a first inductor bridging between the first and second dies;
a second inductor coupled to the first inductor and disposed on the second die; and
a metal-insulator-metal capacitor disposed on the second die, and having a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive plate.
12. The power amplifier according to claim 11 , wherein the second die comprises GaAs.
13. The power amplifier according to claim 11 , wherein the second die is between about 75 and about 200 μm in thickness.
14. The power amplifier according to claim 11 , wherein the first inductor comprises a plurality of bond wires, and the second inductor comprises a plurality of metal strips.
15. The power amplifier according to claim 14 , wherein each of the metal strips is more than 8 μm in thickness, and more than 40 μm in width.
16. The power amplifier according to claim 14 , wherein each of the bond wires is between about 10 mils and about 30 mils in height.
17. The power amplifier according to claim 11 , wherein the first die is selected from the group consisting of an LDMOS and a III-V compound semiconductor die.
18. The power amplifier according to claim 11 , wherein the second die has a via hole formed therethrough between the conductive plate and the metal-insulator-metal capacitor second metal layer, the via hole filled with an interconnect metal.
19. The power amplifier according to claim 11 , wherein the second inductor, and the metal-insulator-metal capacitor first and second metal layers are formed from the same materials.
20. The power amplifier according to claim 11 , wherein the second die comprises an insulating or semi-insulating substrate.