IP Library Granted Patent US 7,811,382
Granted Patent B2
US 7,811,382 · App. 11/421,009 · Granted Oct 12, 2010

Method for forming a semiconductor structure having a strained silicon layer

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Quick Facts
Patent No.
US 7,811,382
App. No.
11/421,009
Granted
Oct 12, 2010
Kind
B2
Abstract

A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.

Claims (66)

1. A method for making a semiconductor structure, comprising:

providing a donor wafer comprising:

a silicon layer that has relaxed strain;

a graded silicon germanium (SiGe) layer on the silicon layer; and

a SiGe buffer layer on the graded SiGe layer, wherein the SiGe buffer layer has relaxed strain and has a germanium concentration of at least 30 percent;

epitaxially growing a first silicon layer on the SiGe buffer layer to a thickness of less than 200 Angstroms, wherein the first silicon layer has tensile strain;

forming a first dielectric layer on the first silicon layer;

performing an implant to form a cleave line in the SiGe buffer layer;

providing a handle wafer comprising:

a semiconductor substrate; and

second dielectric layer on the semiconductor substrate;

bonding the second dielectric layer to the first dielectric layer;

cleaving the SiGe buffer layer along the cleave line to leave the first dielectric layer, the first silicon layer, and a portion of the SiGe buffer layer attached to the handle wafer;

removing the portion of the SiGe layer to expose the first silicon layer;

epitaxially growing silicon on the first silicon layer by applying trisilane at a temperature below 650 degrees Celsius to form a low temperature silicon layer on the first silicon layer to a thickness in excess of 300 Angstroms, wherein the low temperature silicon layer has tensile strain; and

forming a transistor having a gate over the low temperature silicon layer, a first source/drain in the low temperature silicon layer, and a second source/drain in the low temperature in the low temperature silicon layer, wherein the gate is over a space between the first and second source/drains.

2. The method of claim 1 , wherein the step of epitaxially growing silicon forms the low temperature silicon layer to a thickness of at least three times thicker than the first silicon layer and with biaxial tensile strain.

3. The method of claim 1 , wherein the step of epitaxially growing silicon further comprises applying hydrogen with the trisilane.

4. The method of claim 1 , wherein the step of epitaxially growing silicon further comprises applying helium with the trisilane.

5. The method of claim 1 , wherein the step of epitaxially growing silicon forms the low temperature silicon layer to a thickness in excess of 500 Angstroms.

6. The method of claim 5 , wherein the step of epitaxially growing silicon forms the low temperature silicon layer to a thickness of about 1000 Angstroms.

7. The method of claim 1 , wherein the forming the first dielectric layer comprises forming the first dielectric layer of high temperature oxide formed from dichlorosilane and nitrous oxide at a temperature of at least 750 degrees Celsius.

8. The method of claim 1 , wherein the forming the first dielectric layer comprises forming the first dielectric layer of high temperature oxide formed from disilane and nitrous oxide at a temperature between about 800 and 850 degrees Celsius.

9. The method of claim 1 , wherein the step of epitaxially growing the low temperature silicon layer is performed at a temperature not greater than 500 degrees Celsius.

10. A method of forming a semiconductor structure, comprising:

providing a donor wafer comprising:

a silicon layer;

a graded silicon germanium (SiGE) layer on the silicon layer; and

a SiGe buffer layer on the graded SiGe layer;

epitaxially growing a first silicon layer on the SiGe buffer layer;

forming a first dielectric layer on the first silicon layer;

providing a handle wafer comprising:

a supporting substrate; and

second dielectric layer on the supporting substrate;

bonding the second dielectric layer to the first dielectric layer;

cleaving the SiGe buffer layer to leave the first dielectric layer, the silicon layer, and a portion of the SiGe buffer layer attached to the handle wafer;

removing the portion of the SiGe layer to expose the first silicon layer;

epitaxially growing silicon on the first silicon layer by applying trisilane at a temperature below 650 degrees Celsius to form a low temperature silicon layer on the first silicon layer; and

forming a transistor over and in the low temperature silicon layer;

wherein:

the step of epitaxially growing the first silicon layer grows the first silicon layer to thickness of less than 200 Angstroms; and

the step of epitaxially growing silicon comprises growing the low temperature silicon to a thickness of greater than 500 Angstroms at a temperature of not greater than 500 degrees Celsius.

11. The method of claim 10 , wherein

the step of forming the first dielectric comprises reacting dichlorosilane and nitrous oxide at a temperature of at least 750 degrees Celsius.

12. The method of claim 10 , wherein:

the step of providing the donor wafer provides the SiGe buffer layer at a germanium concentration not less than 30 percent and the silicon layer at a relaxed strain;

the step of epitaxially growing the first silicon layer grows the first silicon layer to achieve a biaxial tensile strain; and

the step of epitaxially growing silicon comprises growing the low temperature silicon with a biaxial tensile strain.

13. The method of claim 10 , wherein the forming the first dielectric layer comprises forming the first dielectric layer of high temperature oxide formed from dichorosilane and nitrous oxide at a temperature between about 800 and 850 degrees Celsius.

14. A method of forming a semiconductor structure, comprising:

providing a donor wafer comprising a silicon germanium (SiGe) buffer layer having relaxed strain;

epitaxially growing a first silicon layer on the SiGe buffer layer;

forming a first dielectric layer on the first silicon layer by applying disilane and nitrous oxide at a temperature of at least 750 degrees Celsius;

providing a handle wafer comprising:

a supporting substrate; and

an oxide layer on the supporting substrate;

bonding the first dielectric layer to the oxide layer;

cleaving the SiGe buffer layer to leave the first dielectric layer, the first silicon layer, and a portion of the SiGe buffer layer attached to the handle wafer;

removing the portion of the SiGe buffer layer to expose the first silicon layer;

epitaxially growing silicon on the first silicon layer to form a second silicon layer on the first silicon layer; and

forming a transistor in and over the second silicon layer;

wherein:

the step of providing the donor wafer provides the SiGe buffer layer at a germanium concentration not less than 30 percent;

the step of epitaxially growing the first silicon layer grows the first silicon layer to a thickness of less than 200 Angstroms with a biaxial tensile strain; and

the step of epitaxially growing silicon comprises growing the second silicon layer to a thickness of greater than 500 Angstroms at a temperature of not greater than 500 degrees Celsius with a biaxial tensile strain.

15. The method of claim 14 , wherein the forming the first dielectric layer occurs at a temperature between about 800 and 850 degrees Celsius.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
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From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
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To: NXP B.V.
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RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
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SECURITY AGREEMENT Recorded May 13, 2010
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SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
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From: SADAKA, MARIAM G.; BARR, ALEXANDER L.; NGUYEN, BICH-YEN; THEAN, VOON-YEW; WHITE, TED R.
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