State retention power gating latch circuit
View Patent ↗A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power from the latch when the power gate signal is asserted and the latch is in a predetermined state. The method may include any one or more of pulling a node of the latch to a selected state while the power gate signal is asserted to ensure that the latch powers up in the predetermined state, providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof, switching a supply voltage to a power input of the latch based on a state of the output of the logic gate, and closing a switch to pull a node of the latch low.
1. A state retention power gating latch circuit, comprising:
a latch having a power input; and
an imbalance circuit having a first input receiving a power gate signal, a second input coupled to a selected node of said latch, a third input coupled to a supply voltage, and an output coupled to said power input of said latch;
wherein said imbalance circuit is operative to power down said latch while said power gate signal is asserted when said latch is in a predetermined state and to power up said latch into said predetermined state when said power gate signal is negated.
2. The state retention power gating latch circuit of claim 1 , wherein said latch comprises an inverter loop comprising an inverter having an input and an output, and wherein said selected node is a selected one of said input and output of said inverter.
3. The state retention power gating latch circuit of claim 1 , wherein said imbalance circuit comprises:
a logic gate having a first input receiving said power gate signal, a second input coupled to said selected node of said latch, and an output;
a first switch having a first controlled electrode coupled to said supply voltage, a second controlled electrode coupled to said power input of said latch, and a control electrode coupled to said output of said logic gate;
a second switch having a first controlled electrode coupled to said power input of said latch, a second controlled electrode coupled to a reference supply voltage, and a control electrode coupled to said output of said logic gate; and
a third switch having a first controlled electrode coupled to said selected node of said latch, a second controlled electrode coupled to said reference supply voltage, and a control electrode coupled to said power input of said first inverter loop.
4. The state retention power gating latch circuit of claim 3 , wherein said second and third switches are each implemented as higher voltage threshold devices with reduced leakage current.
5. The state retention power gating latch circuit of claim 3 , wherein:
said latch comprises an inverter loop comprising an inverter having an input and an output;
wherein said selected node is said output of said inverter;
wherein said second input of said logic gate is coupled to said output of said inverter;
wherein said logic gate switches said first, second and third switches to power down said inverter loop when said output of said inverter is low when said power gate signal is asserted in which said third switch keeps said output of said inverter low while said power gate signal is asserted; and
wherein said logic gate switches said first, second and third switches to power up said inverter loop when said power gate signal is negated.
6. The state retention power gating latch circuit of claim 3 , wherein:
said latch comprises an inverter loop comprising an inverter having an input and an output;
wherein said selected node is said input of said inverter;
wherein said second input of said logic gate is coupled to said input of said inverter;
wherein said logic gate switches said first, second and third switches to power down said inverter loop when said output of said inverter is high when said power gate signal is asserted in which said third switch keeps said input of said inverter low while said power gate signal is asserted; and
wherein said logic gate switches said first, second and third switches to power up said inverter loop when said power gate signal is negated.
7. The state retention power gating latch circuit of claim 1 , wherein:
said latch comprises a plurality of latches each having a power input;
wherein said imbalance circuit comprises a plurality of imbalance circuits, each having a first input receiving said power gate signal, a second input coupled to a selected node of a corresponding one of said plurality of latches, a third input coupled to said supply voltage, and an output coupled to said power input of a corresponding latch; and
wherein each imbalance circuit is operative to power down a corresponding latch while said power gate signal is asserted when said corresponding latch is in a first predetermined state and to maintain power to said corresponding latch while said power gate signal is asserted when said corresponding latch is in a second predetermined state.
8. A latching circuit, comprising:
a slave latch having an input, an output and a power input; and
a state retention power gating circuit having a first input receiving a power gate signal, a second input coupled to a selected one of said input and output of said slave latch, a third input coupled to a first supply voltage, and an output coupled to said power input of said slave latch;
wherein said state retention power gating circuit is operative to power down said slave latch while said power gate signal is asserted when said slave latch is in a predetermined state and to power up said slave latch into said predetermined state when said power gate signal is negated.
9. The state retention power gating latching circuit of claim 8 , wherein said state retention power gating circuit comprises:
a NOR gate having a first input receiving said power gate signal, a second input coupled to said selected one of said input and output of said slave latch, and an output;
a first P-channel metal-oxide semiconductor (PMOS) transistor having a source coupled to said first supply voltage, a drain coupled to said power input of said slave latch, and a gate coupled to said output of said NOR gate;
an N-channel MOS (NMOS) transistor having a drain coupled to said power input of said slave latch, a source coupled to a reference supply voltage, and a gate coupled to said output of said NOR gate; and
a second PMOS transistor having a source coupled to said second input of said NOR gate, a drain coupled to said reference supply voltage, and a gate coupled to said power input of said slave latch.
10. The state retention power gating latching circuit of claim 9 , wherein said second input of said NOR gate is coupled to said output of said slave latch, wherein said NOR gate switches said first and second PMOS transistors and said NMOS transistor to power down said slave latch when said output of said slave latch is low when said power gate signal is asserted in which said second PMOS transistor keeps said output of said slave latch low while said power gate signal is asserted, and wherein said NOR gate switches said first and second PMOS transistors and said NMOS transistor to power up said slave latch when said power gate signal is negated.
11. The state retention power gating latching circuit of claim 9 , wherein said second input of said NOR gate is coupled to said input of said slave latch, wherein said NOR gate switches said first and second PMOS transistors and said NMOS transistor to power down said slave latch when said output of said slave latch is high when said power gate signal is asserted in which said second PMOS transistor keeps said input of said slave latch low while said power gate signal is asserted, and wherein said NOR gate switches said first and second PMOS transistors and said NMOS transistor to power up said slave latch when said power gate signal is negated.
12. The state retention power gating latching circuit of claim 8 , further comprising a master latch having an output, a first switch interposed between said output of said master latch and said input of said slave latch and a second switch interposed between said output of said second inverter and said input of said first inverter of said slave latch.
13. A method of power gating a latch, comprising:
detecting a state of the latch;
detecting a power gate signal;
providing power to the latch while the power gate signal is negated; and
removing power from the latch when the power gate signal is asserted and the latch is in a first predetermined state.
14. The method of claim 13 , further comprising pulling a node of the latch to a second predetermined state while the power gate signal is asserted to ensure that the latch powers up in the first predetermined state.
15. The method of claim 14 , wherein said pulling a node of the latch to a second predetermined state comprises closing a switch to pull the node low.
16. The method of claim 15 , said latch comprising an inverter having an input and an output, wherein said pulling a node of the latch to a second predetermined state comprises pulling the output of the inverter low.
17. The method of claim 15 , said latch comprising an inverter having an input and an output, wherein said pulling a node of the latch to a second predetermined state comprises pulling the input of the inverter low.
18. The method of claim 13 , further comprising maintaining providing power to the latch when the power gate signal is asserted and the latch is in a second predetermined state.
19. The method of claim 13 , wherein said detecting a state of the latch and a power gate signal comprises providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof.
20. The method of claim 19 , wherein said providing power to the latch and removing power from the latch comprises switching a supply voltage to a power input of the latch based on a state of the output of the logic gate.