Source side injection storage device and method therefor
View Patent ↗A memory charge storage device has regions of sacrificial material overlying a substrate ( 12 ). For each memory cell a first doped region ( 20 ) and a second doped region ( 24 ) are formed within the substrate and on opposite sides of one ( 16 ) of the regions of sacrificial material. A discrete charge storage layer ( 28 ) overlies the substrate and is between the regions of sacrificial material. In one form a control electrode ( 34 ) is formed per memory cell overlying the substrate with an underlying substrate diffusion and laterally adjacent one of the regions of sacrificial material. A third substrate diffusion ( 60 ) is positioned between the two control electrodes. In another form two control electrodes are formed per memory cell with a substrate diffusion underlying each control electrode. In both forms a select electrode ( 64 ) overlies and is between both of the two control electrodes.
1. A method for forming a storage device structure comprising:
providing a substrate of a first conductivity type;
forming overlying regions of sacrificial material;
forming a first doped region of a second conductivity type opposite the first conductivity type and a second doped region of the second conductivity type within the substrate and on opposite sides of one of the regions of sacrificial material;
after the steps of forming the overlying regions and forming the first doped region, forming a discrete charge storage layer overlying the substrate and between the regions of the sacrificial material;
forming a first conductive control electrode and a second conductive control electrode overlying the substrate and on opposite sides of the one of the regions of sacrificial material; and
forming a conductive select electrode overlying and between both of the first conductive control electrode and the second conductive control electrode.
2. The method of claim 1 further comprising:
forming a third doped region of the second conductivity type between the first doped region and the second doped region and between the first conductive control electrode and the second conductive control electrode.
3. The method of claim 2 further comprising:
forming the conductive select electrode also over the third doped region.
4. The method of claim 1 further comprising:
forming disposable sidewall spacers adjacent the overlying regions prior to forming the first doped region and the second doped region; and
removing the disposable sidewall spacers after forming the first doped region and the second doped region.
5. The method of claim 1 further comprising:
using nanoclusters to form the discrete charge storage layer.
6. The method of claim 1 further comprising:
using nitride as the sacrificial material.
7. The method of claim 1 wherein forming the discrete charge storage layer overlying the substrate between the sacrificial material further comprises depositing a layer of nanoclusters and removing portions of the layer that are not underlying the first conductive control electrode and the second conductive control electrode.
8. A method for forming a storage device structure comprising
providing a substrate;
forming a plurality of regions of sacrificial material overlying the substrate;
forming a disposable sidewall spacer on each of the regions of sacrificial material to decrease distance separating the regions of sacrificial material;
forming a plurality of diffusions in portions of the substrate that are not covered by either a disposable sidewall spacer or the regions of sacrificial material;
removing the disposable sidewall spacer on each of the regions of sacrificial material;
depositing a discrete charge storage layer and patterning the discrete storage layer to form a plurality of discrete charge storage materials that overlie each of the plurality of diffusions;
forming a plurality of control gates, each of the plurality of control gates overlying one of the plurality of discrete charge storage materials;
forming a gate dielectric layer in contact with a portion of the plurality of control gates; and
forming a select gate overlying each of the plurality of control gates and laterally between each of the plurality of control gates, wherein adjacent memory cells share the select gate.
9. The method of claim 8 further comprising:
forming another plurality of diffusions in the substrate, between the regions of sacrificial material and underlying the select gate, each of the another plurality of diffusions functioning as current electrode.
10. The method of claim 8 further comprising:
biasing the storage device structure to permit each of the plurality of diffusions to function as a source for a first of two storage bits in a single memory cell and as a drain for a second of the two storage bits.
11. The method of claim 8 further comprising:
forming removable sidewall spacers around each of the plurality of control gates prior to forming the another plurality of diffusions in the substrate, the removable sidewall spacers substantially centering the another plurality of diffusions in the substrate between the plurality of control gates; and
removing the removable sidewall spacers.