Method and system for signal error determination and correction in a flexray communication system
View Patent ↗A signal error determination and correction system is provided which comprises an error correction value calculation means which processes a predetermined segment of a signal to calculate an error correction value, and a signal correction means and prediction which applies the error correction value to at least part of the signal to correct the part of the signal. The invention further provides a method of signal error determination and correction.
1. A method of determining and correcting an error in a signal comprising a plurality of bits, the method comprising the steps of:
processing a predetermined segment of a signal to calculate an error correction value; and
applying the error correction value to at least part of the signal to correct a value of one or more of the bits in the part of the signal;
processing the predetermined segment of the signal comprises measuring the length of the predetermined segment of the signal; and
subtracting the measured length from an expected length of the predetermined segment to calculate the error correction value.
2. A method as claimed in claim 1 , wherein measuring the length of the predetermined segment of the signal comprises taking samples of the signal, ascertaining a start point of the predetermined segment of the signal, ascertaining an end point of the predetermined segment of the signal, and measuring the length of the predetermined segment of the signal to be the number of signal samples taken between the start point and the end point.
3. A method as claimed in claim 2 which comprises determining the expected length of the predetermined segment of the signal, by calculating a product of a number of samples taken per bit of the signal, and the number of bits in the predetermined segment of the signal.
4. A method as claimed in claim 2 , wherein the signal comprises a frame and the predetermined segment of the signal is the FSS and the first bit of the BSS of the frame.
5. A method as claimed in claim 2 , wherein applying the error correction value to one or more of the bits of the signal to correct the one or more bits, comprises monitoring the logic state values of the expected number of samples in one of the one or more bits, and if a rising edge is detected within the samples, counting the number of samples from the rising edge to the end of the samples, adding the error correction value to the counted number of samples, and if the result is greater than or equal to a predetermined threshold value, assigning a high logic state to the bit, otherwise assigning a low logic state to the bit.
6. A method as claimed in claim 1 , wherein the signal comprises a frame and the predetermined segment of the signal is the FSS and the first bit of the BSS of the frame.
7. A method as claimed in claim 1 , wherein applying the error correction value to one or more of the bits of the signal to correct the one or more bits, comprises monitoring the logic state values of the expected number of samples in one of the one or more bits, and if a rising edge is detected within the samples, counting the number of samples from the rising edge to the end of the samples, adding the error correction value to the counted number of samples, and if the result is greater than or equal to a predetermined threshold value, assigning a high logic state to the bit, otherwise assigning a low logic state to the bit.
8. A method as claimed in claim 7 , wherein applying the error correction value to one or more of the bits of the signal to correct the bit, comprises monitoring the logic state values of the expected number of samples in the bit, and if a falling edge is detected within the samples, assigning a low logic state to the bit.
9. A method as claimed in claim 8 , wherein applying the error correction value to one or more of the bits of the signal to correct the bit, comprises monitoring the logic state values of the expected number of samples in the bit, and if no edge is detected within the samples of the bit, assigning a logic state to the bit which is the same as that predicted for a previous bit.
10. A method as claimed in claim 7 , wherein applying the error correction value to one or more of the bits of the signal to correct the bit, comprises monitoring the logic state values of the expected number of samples in the bit, and if no edge is detected within the samples of the bit, assigning a logic state to the bit which is the same as that predicted for a previous bit.
11. A method as claimed in claim 7 , which further comprises predicting a logic state of a bit following the bit to which the error correction value has been applied.
12. A signal error determination and correction system comprising;
an error correction value calculation means which processes a predetermined segment of a signal comprising a plurality of bits to calculate an error correction value, and
a signal correction means which applies the error correction value to at least part of the signal to correct one or more of the bits in the part of the signal the error correction value calculation means processes the predetermined segment of the signal by measuring the length of the predetermined segment of the signal, and subtracting the measured length from an expected length of the predetermined segment to calculate the error correction value.
13. A system as claimed in claim 12 , further comprising a sampling means which takes samples of the signal, and wherein the error correction value calculation means measures the length of the predetermined segment of the signal using the samples of the signal, ascertains a start point of the predetermined segment of the signal, ascertains an end point of the predetermined segment of the signal, and measures the length of the predetermined segment of the signal to be the number of signal samples taken between the start point and the end point.
14. A system as claimed in claim 13 , wherein the signal correction means corrects one or more of the bits, by monitoring the logic state values of the expected number of samples in the one of the one or more bits, and if a rising edge is detected within the samples, counting the number of samples from the rising edge to the end of the samples, adding the error correction value to the counted number of samples, and if the result is greater than or equal to a predetermined threshold value, assigning a high logic state to the bit, otherwise assigning a low logic state to the bit.
15. A system as claimed in claim 12 , wherein the signal correction means corrects one or more of the bits, by monitoring the logic state values of the expected number of samples in the one of the one or more bits, and if a rising edge is detected within the samples, counting the number of samples from the rising edge to the end of the samples, adding the error correction value to the counted number of samples, and if the result is greater than or equal to a predetermined threshold value, assigning a high logic state to the bit, otherwise assigning a low logic state to the bit.
16. A system as claimed in claim 15 , wherein the signal correction means corrects the one or more bits, by monitoring the logic state values of the expected number of samples in the bit, and if a falling edge is detected within the samples, assigning a low logic state to the bit.
17. A system as claimed in claim 16 , wherein the signal correction means corrects one or more bits, by monitoring the logic state values of the expected number of samples in the bit, and if no edge is detected within the samples of the bit, assigning a logic state to the bit which is the same as that predicted for a previous bit.
18. A system as claimed in claim 16 , which the signal correction means further comprises a signal prediction means which predicts a logic state of a bit following the bit to which the error correction value has been applied.
19. A system as claimed in claim 15 , wherein the signal correction means corrects one or more bits, by monitoring the logic state values of the expected number of samples in the bit, and if no edge is detected within the samples of the bit, assigning a logic state to the bit which is the same as that predicted for a previous bit.
20. A system as claimed in claim 15 , which the signal correction means further comprises a signal prediction means which predicts a logic state of a bit following the bit to which the error correction value has been applied.