Electronic device including dielectric layer, and a process for forming the electronic device
View Patent ↗A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO 2 ) (1-x) (ZrO 2 ) x , wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.
1. An electronic device comprising:
a gate dielectric layer comprising:
oxygen;
a first metallic element; and
a second metallic element different from the first element,
wherein;
the first metallic element has a single oxidation state and an oxidation state value;
the second metallic element has the single oxidation state and the oxidation state value;
within the dielectric layer, a number of first metallic element atoms divided by a sum of the first metallic element atoms and second metallic element atoms is greater than 0.067; and
within the dielectric layer, a number of second metallic element atoms divided by the sum of the first metallic element atoms and the second metallic element atoms is greater than 0.067;
a first gate electrode within a PMOS portion of the electronic device; and
a second gate electrode within an NMOS portion of the electronic device, wherein a composition of the second gate electrode is different from a composition of the first gate electrode.
2. The electronic device of claim 1 , wherein:
the first and second metallic elements are capable of forming a first metallic oxide and a second metallic oxide, respectively;
the first metallic oxide can only have one or more structures selected from a group consisting of a set of structures; and
the second metallic oxide can only have one or more structures selected from a group consisting of the set of structures.
3. The electronic device of claim 1 , wherein the first metallic oxide and the second metallic oxide are substantially miscible with respect to each other.
4. The electronic device of claim 1 , wherein the first metallic element is Hf, and the second metallic element is Zr.
5. The process of claim 1 , wherein the gate dielectric layer comprises an alloy, wherein the alloy is (M1 y O z ) (1-x) (M2 y O z ) x , wherein:
M1 is the first metallic element;
M2 is the second metallic element;
x has a value between 0 and 1; and
y and z are integer values for a stoichiometric compound.
6. A process for forming an electronic device comprising:
forming a dielectric layer over a workpiece using an atomic layer deposition, wherein:
the dielectric layer comprises:
oxygen;
a first metallic element; and
a second metallic element different from the first element,
wherein:
the first metallic element has a single oxidation state and an oxidation state value; and
the second metallic element has the single oxidation state and the oxidation state value,
the dielectric layer comprises more than 0.067 atomic % of the first metallic element; and
the dielectric layer comprises more than 0.067 atomic % of the second metallic element; and
forming an electrode over the dielectric layer.
7. The process of claim 6 , wherein:
the first and second metallic elements are capable of forming a first metallic oxide and a second metallic oxide, respectively;
the first metallic oxide can only have one or more structures selected from a group consisting of a set of structures; and
the second metallic oxide can only have one or more structures selected from a group consisting of the set of structures.
8. The process of claim 6 , wherein forming the dielectric layer comprises depositing the dielectric layer within a chamber, wherein depositing comprises:
performing a sequence of actions comprising:
exposing a surface of a workpiece to a precursor while the workpiece is within the chamber, wherein the precursor comprises the first and second metallic elements;
purging the chamber;
exposing the first and second metallic elements to an oxygen-containing species while the workpiece is within the chamber;
purging the chamber; and
if needed or desired, iterating the sequence of actions at least until a predetermined thickness of the dielectric layer is achieved.
9. The process of claim 6 , wherein forming the dielectric layer comprises depositing the dielectric layer within a chamber, wherein depositing comprises:
performing a sequence of actions comprising:
exposing a surface of a workpiece to a first precursor while the workpiece is within the chamber, wherein the first precursor comprises the first metallic element;
purging the chamber;
exposing the first metallic element to a first oxygen-containing species to form the first metallic oxide;
purging the chamber; and
exposing the first metallic oxide to a second precursor while the workpiece is within the chamber, wherein the second precursor comprises the second metallic element;
purging the chamber;
exposing the second metallic element to an oxygen-containing species;
purging the chamber; and
if needed or desired, iterating the sequence of actions at least until a predetermined thickness of the dielectric layer is achieved.
10. The process of claim 6 , wherein the first metallic element is Hf, and the second metallic element is Zr.
11. The process of claim 10 , wherein the dielectric layer comprises an alloy, wherein the alloy is (HfO 2 ) (1-x) (ZrO 2 ) x , wherein x has a value between 0 and 1.
12. The process of claim 6 , wherein the dielectric layer comprises an alloy, wherein the alloy is (M1 y O z ) (1-x) (M2 y O z ) x , wherein:
M1 is the first metallic element;
M2 is the second metallic element;
x has a value between 0 and 1; and
y and z are integer values for a stoichiometric compound.
13. An electronic device comprising:
a gate dielectric layer that includes grains, wherein:
the gate dielectric layer comprises a material that is capable of affecting sizes of the grains or a size distribution of the grains, wherein the gate dielectric layer comprises more than 0.067 atomic % of atoms from the material;
the material comprises Zr; and
the gate dielectric layer further comprises Hf; and
a first gate electrode within a PMOS portion of the electronic device; and
a second gate electrode within an NMOS portion of the electronic device, wherein a composition of the second gate electrode is different from a composition of the first gate electrode.
14. The electronic device of claim 13 , wherein the gate dielectric layer comprises at least 10 atomic % oxygen.
15. The electronic device of claim 14 , wherein:
the first metallic element has a single oxidation state and an oxidation state value;
the second metallic element has the single oxidation state and the oxidation state value;
the first and second metallic elements are capable of forming a first metallic oxide and a second metallic oxide, respectively;
the first metallic oxide can only have one or more structures selected from a group consisting of a set of structures; and
the second metallic oxide can only have one or more structures selected from a group consisting of the set of structures.
16. The electronic device of claim 15 , wherein the gate dielectric layer first metallic oxide and the second metallic oxide are miscible with respect to each other.
17. The electronic device of claim 14 , further comprising:
a substrate; and
an interface layer lying between the substrate and the gate dielectric layer, wherein the interface layer comprises O, Si, Hf, and Zr.
18. The electronic device of claim 13 , wherein the gate dielectric layer consists essentially of O, Hf, and Zr.
19. The electronic device of claim 13 , wherein the gate dielectric layer further comprises Si, Ge, C, N, Al, or any combination thereof.
20. The electronic device of claim 13 , wherein the gate dielectric layer comprises an alloy, wherein the alloy is (HfO 2 ) (1-x) (ZrO 2 ) x , wherein x has a value between 0 and 1.