Granted Patent B2

US 7,638,995 · App. 11/038,746 · Granted Dec 29, 2009

Abstract

Claims (34)

1. A circuit for generating an output voltage at an output thereof, the circuit comprising:

a node configured to be coupled to said output;

a capacitor having a first terminal configured to be coupled to a reference potential and having a second terminal coupled to said node; and

a switchable current source coupled to said node for intermittently charging said capacitor until the output voltage is reached, said switchable current source comprising:

a current source;

a switch having a first electrode coupled in series with said current source, a second electrode coupled to said node, and a gate electrode; and

a clock generator having an output coupled to said gate electrode for periodically turning said switch ON so as to conduct current from said current source to said capacitor.

2. A circuit according to claim 1 , wherein said clock generator comprises:

a binary counter; and

a decoder coupled to said binary counter for decoding a specific state thereof.

3. A circuit according to claim 2 , wherein said binary counter comprises:

at least two reset-set (RS) latches coupled in series, each of said at least two RS latches having an output, a set input, and a reset input, said output of a preceeding RS latch of said at least two RS latches coupled to said reset input of said preceeding RS latch and to said set input of a subsequent RS latch, said set input of a first RS latch of said at least two RS latches configured to receive said second signal; and

a NAND gate having inputs coupled to different ones of said outputs of said at least two RS latches and having an output coupled to said gate electrode.

4. A circuit according to claim 3 , wherein said clock generator comprises n number of RS latches, said capacitor has a capacitance C, said current source is configured to output a reference current I ref , and

wherein said switchable current source pulses an effective reference current, I ref , for each period dt, such that

I ref (eff)= I ref /2 (n+1) and dt+C×dV× 2 (n+1) /I ref .

5. A circuit according to claim 1 , wherein said capacitor has a capacitance less than about 100 pF.

6. A circuit according to claim 1 , wherein said switchable current source is configured to output a reference current I ref of equal to or greater than about 1 μA.

7. A voltage regulation circuit comprising:

a voltage regulator having an input and configured to generate a supply voltage at an output thereof;

a node coupled to said input;

a capacitor having a first terminal configured to be coupled to a reference potential and having a second terminal coupled to said node; and

a switchable current source coupled to said node for periodically charging said capacitor until a predetermined input voltage is reached, said switchable current source comprising:

a voltage-controlled current source;

a switch having a first electrode coupled in series with said current source, a second electrode coupled to said node, and a gate electrode configured to selectively conduct current from said first electrode to said second electrode; and

a clock generator coupled to said gate electrode, said clock generator configured to periodically transmit an enable signal to said gate electrode for periodically turning said switch ON.

8. A voltage regulation circuit according to claim 7 , wherein said reference potential is a ground.

9. A voltage regulation circuit according to claim 7 , wherein said switch is a transistor.

10. A voltage regulation circuit according to claim 7 , wherein said clock generator is configured to receive a system clock signal, said clock generator comprising:

at least two reset-set (RS) latches coupled in series, each of said at least two RS latches having an output, a set input, and a reset input, said output of a preceeding RS latch of said at least two RS latches coupled to said reset input of said preceeding RS latch and to said set input of a subsequent RS latch, said set input of a first RS latch of said at least two RS latches configured to receive said system clock signal; and

a NAND gate having an input coupled to different ones of said outputs of said at least two RS latches and having an output coupled to said gate electrode.

11. A voltage regulation circuit according to claim 7 , wherein said clock comprises n number of RS latches, said capacitor has a capacitance C, said current source is configured to output a reference current I ref , and wherein said transistor pulses an effective reference current, I ref (eff), for each period dt, such that I ref (eff)=I ref /2 (n+1) and dt=C×dV×2 (n+1) /I ref .

12. A voltage regulation circuit according to claim 7 , wherein said capacitor has a capacitance less than about 100 pF.

13. A voltage regulation circuit according to claim 7 , wherein said switchable current source is configured to output a reference current I ref equal to or greater than about 1 μA.

Assignments (18)