pHEMT with barrier optimized for low temperature operation
View Patent ↗In one embodiment, a semiconductor device ( 500 ) includes a buffer layer ( 504 ) formed over a substrate ( 502 ). An Al x Ga 1−x As layer ( 506 ) is formed over the buffer layer ( 504 ) and has a first doped region ( 508 ) formed therein. An In x Ga 1−x As channel layer ( 512 ) is formed over the Al x Ga 1−x As layer ( 506 ). An Al x Ga 1−x As layer ( 518 ) is formed over the In x Ga 1−x As channel layer ( 512 ), and the Al x Ga 1−x As layer ( 518 ) has a second doped region formed therein. A GaAs layer ( 520 ) having a first recess is formed over the Al x Ga 1−x As layer ( 518 ). A control electrode ( 526 ) is formed over the Al x Ga 1−x As layer ( 518 ). A doped GaAs layer ( 524 ) is formed over the undoped GaAs layer ( 520 ) and on opposite sides of the control electrode ( 526 ) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device ( 500 ) maintains linear operation over a wide temperature range.
1. A semiconductor device comprising:
a substrate;
a buffer layer formed over the substrate;
a bottom layer comprising Al x Ga 1−x As formed over the buffer layer, the bottom layer having a first doped region formed therein, wherein the first doped region comprises a layer of GaAs, a layer of Si, and a layer of GaAs;
an In x Ga 1−x As layer formed over the bottom layer;
an Al x Ga 1−x As layer formed over the In x Ga 1−x As layer, the Al x Ga 1−x As layer having a second doped region formed therein, wherein the second doped region comprises a layer of GaAs, a layer of Si, and a layer of GaAs;
an undoped GaAs layer formed over the Al x Ga 1−x As layer, the undoped GaAs layer having a first recess formed therein that exposes a portion of the Al x Ga 1−x As layer;
a doped GaAs layer formed over the undoped GaAs layer, the doped GaAs layer having a second recess therein that exposes a portion of the undoped GaAs layer;
a control electrode having opposite ends formed within the first recess of the undoped GaAs layer and within the second recess of the doped GaAs layer; and
first and second current electrodes disposed on the doped GaAs layer proximate opposite ends of the control electrode such that the doped GaAs layer provides current through the first and second current electrodes for the semiconductor device.
2. The semiconductor device of claim 1 wherein the first doped region and the second doped region comprise a first layer of GaAs, a monolayer of Si disposed over the first layer of GaAs, and a second layer of GaAs disposed over the monolayer of Si, and wherein each region is less than approximately 40 Å in thickness.
3. The semiconductor device of claim 2 wherein the first and the second doped regions have a thickness less than approximately 25 Å.
4. The semiconductor device of claim 1 , wherein the GaAs substrate is a semi-insulating substrate.
5. The semiconductor device of claim 1 , further comprising an etch stop layer between the undoped GaAs layer and the doped GaAs layer, wherein the etch stop layer comprises one selected from the group consisting of AlAs and In x Ga 1−x P.
6. The semiconductor device of claim 1 , wherein the control electrode comprises one selected from the group consisting of titanium tungsten nitride (TiWN) and tungsten silicide (WSi).
7. An amplifier comprising:
a transistor comprising:
a substrate;
a buffer layer formed over the substrate;
an Al x Ga 1−x As layer formed over the buffer layer, the Al x Ga 1−x As layer having a first doped region formed therein, wherein the first doped region comprises a layer of GaAs, a layer of Si, and a layer of GaAs;
an In x Ga 1−x As layer formed over the Al x Ga 1−x As layer;
an Al x Ga 1−x As layer formed over the In x Ga 1−x As layer, the Al x Ga 1−x As layer having a second doped region formed therein, wherein the second doped region comprises a layer of GaAs, a layer of Si, and a layer of GaAs;
an undoped GaAs layer formed over the Al x Ga 1−x As layer, the undoped GaAs layer having a first recess formed therein that exposes a portion of the Al x Ga 1−x As layer;
a doped GaAs layer formed over the undoped GaAs layer, the doped GaAs layer having a second recess therein that exposes a portion of the undoped GaAs layer;
a control electrode having opposite ends formed within the first recess of the undoped GaAs layer and within the second recess of the doped GaAs layer; and
first and second current electrodes disposed on the doped GaAs layer proximate opposite ends of the control electrode such that the doped GaAs layer provides current through the first and second current electrodes for the semiconductor device;
a gate bias network coupled to the control electrode of the transistor; and
a drain bias network coupled to the first current electrode.
8. The amplifier of claim 7 wherein the first doped region and the second doped region comprise a first layer of GaAs, a monolayer of Si disposed over the first layer of GaAs, and a second layer of GaAs disposed over the monolayer of Si, and wherein each region is less than approximately 40 Å in thickness.
9. The amplifier of claim 7 , wherein the gate bias network comprises an input for receiving a digital spread sprectrum modulation signal.
10. The amplifier of claim 7 , wherein the digital spread spectrum modulation signal is a wide-band code division multiple access (WCDMA) signal.
11. The amplifier of claim 7 , wherein the transistor further comprises first and second metal source/drain contacts formed on the first and second current electrodes, respectively.
12. The amplifier of claim 7 , wherein the transistor is a pseudomorphic high electron mobility transistor (pHEMT).
13. The amplifier of claim 7 , wherein the control electrode is asymmetrically positioned between the first and second current electrodes.