Method of forming a current controlling device
View Patent ↗A current-controlling device comprising a first conductor, a second conductor, and a tunneling barrier comprising a first insulating layer between the first conductor and the second conductor. The tunneling barrier electrically isolates the first conductor from the second conductor. At least one mobile charge is positionable within the tunneling barrier. The device also includes a gate, wherein a voltage applied to the gate with respect to the substrate (or with respect to a second gate formed on or in the substrate) modulates or moves the mobile charge to a position between the first conductor and the second conductor within the tunneling barrier, thus deforming the shape of the energy barrier between the first conductor and the second conductor. The deformation can cause a current to flow between the conductors when a voltage is present between them due to quantum mechanical tunneling.
1. A method of forming a current-controlling device on a substrate, the method comprising:
forming a first insulating layer on the substrate;
creating a first conductor on the first insulating layer;
shaping the first conductor to form a first tunneling contact area;
forming a second insulating layer on the surface of the first conductor;
creating a second conductor on the first and second insulating layers;
shaping the second conductor to form a second tunneling contact area;
planarizing the first conductor, the second insulating layer, and the second conductor to form a single planarized surface and a tunneling barrier between the first tunneling contact area and the second tunneling contact area, the tunneling barrier comprising the second insulating layer;
forming a third insulating layer on the single planarized surface;
introducing at least one mobile charge within at least one of the insulating layers, the mobile charge positionable within the tunneling barrier; and
creating a gate contact on the third insulating layer.
2. The method of claim 1 , wherein the first insulating layer comprises silicon dioxide.
3. The method of claim 1 , wherein all the insulating layers comprise silicon dioxide.
4. The method of claim 1 , wherein the first conductor comprises n-type or p-type silicon.
5. The method of claim 1 , wherein the planarizing step comprises Chemical Mechanical Planarization.
6. The method of claim 1 , further comprising implanting the at least one mobile charge in an insulating layer.
7. The method of claim 1 , further comprising diffusing the at least one mobile charge in an insulating layer.
8. The method of claim 1 , wherein the at least one mobile charge comprises between 1 and about 100 ions.
9. The method of claim 1 , wherein the tunneling gap is about 10 nanometers wide.
10. A method of forming a current-controlling device on a substrate, the method comprising:
forming a first insulating layer on the substrate;
creating a first layer of doped polycrystalline silicon on the first insulating layer, the first layer of doped polycrystalline silicon comprising n-type or p-type silicon;
shaping the first layer of doped polycrystalline silicon to form a first tunneling contact area;
forming a first silicon dioxide layer on the exposed surface of the first layer of doped polycrystalline silicon, the first silicon dioxide layer comprising between one and about 100 mobile ions;
creating a second layer of doped polycrystalline silicon on the first insulating layer and on the first silicon dioxide layer, the second layer of doped polycrystalline silicon comprising n-type or p-type silicon;
shaping the second layer of doped polycrystalline silicon to form a second tunneling contact area;
planarizing, by Chemical Mechanical Planarization, the first layer of doped polycrystalline silicon, the second insulating layer, and the second layer of doped polycrystalline silicon to form a tunneling gap between the first tunneling contact area and the second tunneling contact area, the gap comprising the first silicon dioxide layer and the mobile ions, the tunneling gap being between about 5 nanometers and about 15 nanometers wide;
forming a second silicon dioxide layer on the planarized surface; and
creating a gate contact layer on the third insulating layer.