Method to improve cache capacity of SOI and bulk
View Patent ↗Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.
1. A static random access memory device, comprising:
a memory comprising an array of memory cells, each memory cell comprising;
a first and second passgate transistor;
a first and second storage node, wherein the first passgate transistor is connected between a first bit line and a first storage node, wherein a gate terminal of the first passgate transistor connects to a word line, and the second passgate transistor is connected between a second bit line and the second storage node, wherein a gate terminal of the second passgate transistor connects to the word line;
a first pull-up transistor, connected between a source voltage and the first storage node, wherein a gate terminal of the first pull-up transistor is connected to the second storage node;
a second pull-up transistor, connected between the source voltage and the second storage node, wherein a gate terminal of the first pull-up transistor is connected to the first storage node;
a first pull-down transistor, connected between the first storage node and a ground, wherein a gate terminal of the first pull-down transistor is connected to the second storage node; and
a second pull-down transistor, connected between the second storage node and the ground, wherein a gate terminal of the second pull-down transistor is connected to the first storage node;
wherein the first and second passgate transistors and the first and second pull-down transistors have first threshold voltages that are substantially the same, and wherein the first and second pull-up transistors have second threshold voltages that are substantially the same, and wherein the first threshold voltages are greater than the second threshold voltages.
2. The memory device of claim 1 , wherein the first threshold voltages are a first voltage that is in a range of about 0.7 V to about 0.3 V and wherein the second threshold voltages are a second voltage that is about 10% lower than the first voltage.
3. The memory device of claim 1 , wherein the first and second access transistors are NFETs, the first and second passgate transistors are NFETs, and wherein the first and second pull-up transistors are PFETs.
4. The memory device of claim 1 , wherein each memory cell has a cell beta ratio of about 2.0 or greater.
5. A static random access memory device, comprising:
a memory comprising an array of memory cells, each memory cell comprising:
a first and second passgate transistor;
a first and second storage node, wherein the first passgate transistor is connected between a first bit line and a first storage node, wherein a gate terminal of the first passgate transistor connects to a word line, and the second passgate transistor is connected between a second bit line and the second storage node, wherein a gate terminal of the second passgate transistor connects to the word line;
a first pull-up transistor, connected between a source voltage and the first storage node, wherein a gate terminal of the first pull-up transistor is connected to the second storage node;
a second pull-up transistor, connected between the source voltage and the second storage node, wherein a gate terminal of the second pull-up transistor is connected to the first storage node;
a first pull-down transistor, connected between the first storage node and a ground, wherein a gate terminal of the first pull-down transistor is connected to the second storage node; and
a second pull-down transistor, connected between the second storage node and the ground, wherein a gate terminal of the second pull-down transistor is connected to the first storage node;
wherein the first and second pull-down transistors, the first and second pull-up transistors and the first and second passgate transistors all have first threshold voltages that are substantially the same, wherein the first threshold voltage is a voltage in a range of about 0.3 V to about 0.7 V.
6. The memory device of claim 5 , wherein the first and second access transistors are NFETs, the first and second passgate transistors are NFETs, and wherein the first and second pull-up transistors are PFETs.
7. The memory device of claim 5 , wherein each memory cell has a cell beta ratio of about 2.0 or greater.
8. A static random access memory device, comprising:
a memory comprising an array of memory cells, each memory cell comprising:
a first and second passgate transistor;
a first and second storage node, wherein the first passgate transistor is connected between a first bit line and a first storage node, wherein a gate terminal of the first passgate transistor connects to a word line, and the second passgate transistor is connected between a second bit line and the second storage node, wherein a gate terminal of the second passgate transistor connects to the word line;
a first pull-up transistor, connected between a source voltage and the first storage node, wherein a gate terminal of the first pull-up transistor is connected to the second storage node;
a second pull-up transistor, connected between the source voltage and the second storage node, wherein a gate terminal of the second pull-up transistor is connected to the first storage node;
a first pull-down transistor, connected between the first storage node and a ground, wherein a gate terminal of the first pull-down transistor is connected to the second storage node; and
a second pull-down transistor, connected between the second storage node and the ground, wherein a gate terminal of the second pull-down transistor is connected to the first storage node;
wherein the first and second passgate transistors have first threshold voltages that are substantially the same, and wherein the first and second pull-up transistors and the first and second pull-down transistors have second threshold voltages that are substantially the same, and wherein the first threshold voltages are greater than the second threshold voltages.
9. The memory device of claim 8 , wherein the first threshold voltages are a first voltage that is in a range of about 0.7 V to about 0.3 V and wherein the second threshold voltages are a second voltage that is about 10% lower than the first voltage.
10. The memory device of claim 8 , wherein the first and second access transistors are NFETs, the first and second passgate transistors are NFETs, and wherein the first and second pull-up transistors are PFETs.
11. The memory device of claim 8 , wherein each memory cell has a cell beta ratio of about 2.0 or greater.