Data processing system and method
View Patent ↗A method for generating at least one error checking code includes creating a modified input data word, including (k+m) bits, by combining an input data word, having n-bits, with at least a previously calculated at least one error checking code, including in-bits, where n≦k, and calculating a first m-bit error checking code from at least a first selected portion of the modified input data word.
1. A method for generating at least one error checking code, comprising:
creating a modified input data word, comprising (k+m) bits, by combining an input data word, having n-bits, with at least a previously calculated at least one error checking code, comprising m-bits, where n≦k; and
calculating a first m-bit error checking code from at least a first selected portion of the modified input data word.
2. A method as claimed in claim 1 , wherein creating the modified input data word comprises deriving the (m+n−1)th to the mth bits of the modified input data word from at least one of the input data word and at least part of the previously calculated at least one error checking code.
3. A method as claimed in claim 2 , wherein creating the modified input data word comprises deriving the (m+n−1)th to the mth bits of the modified input data word from at least one of the input data word and the whole of the previously calculated at least one error checking code.
4. A method as claimed in claim 1 , wherein creating the modified input data word comprises deriving the m least or most significant bits of the modified input data word from at least one of m bits, having a predetermined value, and the previously calculated at least one error checking code.
5. A method as claimed in claim 4 , wherein deriving the m least or most significant bits comprises setting at least the n least or most significant bits of the modified data word to the predetermined value.
6. A method as claimed in claim 5 , wherein deriving the m least or most significant bits comprises setting all of the m least or most significant bits of the modified input data word to the predetermined value.
7. A method as claimed in claim 4 , wherein deriving the m least or most significant bits comprises deriving the (m−n) most or least significant bits of the m least or most significant bits of the modified input data word from the previously calculated at least one error checking code.
8. A method as claimed in claim 1 , wherein the first m-bit error checking code is an intermediate m-bit error checking code, and the generating the at least one error checking code comprises performing a finite field arithmetic operation using the intermediate m-bit error checking code and a second selected portion of the modified input data word to generate the at least one error checking code.
9. A method as claimed in claim 8 , wherein the finite field arithmetic operation comprises at least one of Galois Field (GF) addition or multiplication.
10. A method as claimed in claim 1 , wherein the first m-bit error checking code is an intermediate m-bit error checking code, and the method further comprises generating the at least one error checking code by combining the intermediate m-bit error checking code and a second selected portion of the modified input data word.
11. A method as claimed in claim 1 , further comprising calculating the first m-bit error checking code using a parallel CRC module that has one of a k-bit wide data input and a (k+m)-bit wide data input.
12. A method as claimed in claim 1 , wherein creating a modified input data word comprises, if n<k, creating the modified input data word such that the (k−n) most significant bits comprise a predetermined value.
13. A method as claimed in claim 1 , wherein creating a modified input data word comprises, if n<k, creating the modified input data word such that the (k−n) least significant bits comprise a predetermined value.
14. A method as claimed in claim 1 , further comprising creating a first modified input data word, having (k+m) bits, by combining an input data word, having n bits, with an initialization value.
15. A system for generating at least one error checking code, comprising:
means for creating a modified input data word, comprising (k+m) bits, by combining an input data word, having n-bits, with at least a previously calculated at least one error checking code, comprising m-bits, where n≦k; and
means for calculating a first m-bit error checking code from at least a first selected portion of the modified input data word.
16. A system as claimed in claim 15 , wherein the means for creating the modified input data word comprises means for deriving the (m+n−1)th to the mth bits of the modified input data word from at least one of the input data word and at least part of the previously calculated at least one error checking code.
17. A system as claimed in claim 16 , wherein the means for creating the modified input data word comprises means for deriving the (m+n−1)th to the mth bits of the modified input data word from at least one of the input data word and the whole of the previously calculated at least one error checking code.
18. A system as claimed in claim 15 , wherein the means for creating the modified input data word comprises means for deriving the m least or most significant bits of the modified input data word from at least one of m bits, having a predetermined value, and the previously calculated at least one error checking code.
19. A system as claimed in claim 18 , wherein the means for deriving the m least or most significant bits comprises means for setting at least the n least or most significant bits of the modified data word to the predetermined value.
20. A system as claimed in claim 19 , wherein the means for deriving the m least or most significant bits comprises means for setting all of the m least or most significant bits of the modified input data word to the predetermined value.
21. A system as claimed in claim 18 , wherein the means for deriving the m least or most significant bits comprises means for deriving the (m−n) most or least significant bits of the m least or most significant bits of the modified input data word from the previously calculated at least one error checking code.
22. A system as claimed in claim 15 , wherein the first m-bit error checking code is an intermediate m-bit error checking code, and the means for generating the at least one error checking code comprises means for performing a finite field arithmetic operation using the intermediate m-bit error checking code and a second selected portion of the modified input data word to generate the at least one error checking code.
23. A system as claimed in claim 22 , wherein the finite field arithmetic operation comprises at least one of Galois Field (GF) addition or multiplication.
24. A system as claimed in claim 15 , wherein the first m-bit error checking code is an intermediate m-bit error checking code, and the system further comprises means for generating the at least one error checking code by combining the intermediate m-bit error checking code and a second selected portion of the modified input data word.
25. A system as claimed in claim 15 , further comprising means for calculating the first m-bit error checking code using a parallel CRC module that has one of a k-bit wide data input and a (k+m)-bit wide data input.
26. A system as claimed in claim 15 , wherein the means for creating a modified input data word comprises, if n<k, means for creating the modified input data word such that the (k−n) most significant bits comprise a predetermined value.
27. A system as claimed in claim 15 , wherein the means for creating a modified input data word comprises, if n<k, means for creating the modified input data word such that the (k−n) least significant bits comprise a predetermined value.
28. A system as claimed in claim 15 , further comprising means for creating a first modified input data word, having (k+m) bits, by combining an input data word, having n bits, with an initialization value.
29. A computer program product for generating at least one error checking code, comprising:
a computer readable storage medium having computer readable program code embodied therein, the computer readable program code comprising:
computer readable program code configured to create a modified input data word, comprising (k+m) bits, by combining an input data word, having n-bits, with at least a previously calculated at least one error checking code, comprising m-bits. where n≦k; and
computer readable program code configured to calculate a first m-bit error checking code from at least a first selected portion of the modified input data word.
30. A computer program product as claimed in claim 29 , wherein the computer readable program code configured to create the modified input data word comprises computer readable program code configured to derive the (m+n−1)th to the mth bits of the modified input data word from at least one of the input data word and at least part of the previously calculated at least one error checking code.
31. A computer program product as claimed in claim 30 , wherein the computer readable program code configured to create the modified input data word comprises computer readable program code configured to derive the (m+n−1)th to the mth bits of the modified input data word from at least one of the input data word and the whole of the previously calculated at least one error checking code.
32. A computer program product as claimed in claim 29 , wherein the computer readable program code configured to create the modified input data word comprises computer readable program code configured to derive the m least or most significant bits of the modified input data word from at least one of m bits, having a predetermined value, and the previously calculated at least one error checking code.
33. A computer program product as claimed in claim 32 , wherein the computer readable program code configured to derive the m least or most significant bits comprises computer readable program code configured to set at least the n least or most significant bits of the modified data word to the predetermined value.
34. A computer program product as claimed in claim 33 , wherein the computer readable program code configured to derive the m least or most significant bits comprises computer readable program code configured to set all of the m least or most significant bits of the modified input data word to the predetermined value.
35. A computer program product as claimed in claim 32 , wherein the computer readable program code configured to derive the m least or most significant bits comprises computer readable program code configured to derive the (m−n) most or least significant bits of the m least or most significant bits of the modified input data word from the previously calculated at least one error checking code.
36. A computer program product as claimed in claim 29 , wherein the first m-bit error checking code is an intermediate m-bit error checking code, and the computer readable program code configured to generate the at least one error checking code comprises computer readable program code configured to perform a finite field arithmetic operation using the intermediate m-bit error checking code and a second selected portion of the modified input data word to generate the at least one error checking code.
37. A computer program product as claimed in claim 36 , wherein the finite field arithmetic operation comprises at least one of Galois Field (GF) addition or multiplication.
38. A computer program product as claimed in claim 29 , wherein the first m-bit error checking code is an intermediate m-bit error checking code, and the computer program product further comprises computer readable program code configured to generate the at least one error checking code by combining the intermediate m-bit error checking code and a second selected portion of the modified input data word.
39. A computer program product as claimed in claim 29 , further comprising computer readable program code configured to calculate the first m-bit error checking code using a parallel CRC module that has one of a k-bit wide data input and a (k+m)-bit wide data input.
40. A computer program product as claimed in claim 29 , wherein the computer readable program code configured to create a modified input data word comprises, if n<k, computer readable program code configured to create the modified input data word such that the (k−n) most significant bits comprise a predetermined value.
41. A computer program product as claimed in claim 29 , wherein the computer readable program code configured to create a modified input data word comprises, if n<k, computer readable program code configured to create the modified input data word such that the (k−n) least significant bits comprise a predetermined value.
42. A computer program product as claimed in claim 29 , further comprising computer readable program code configured to create a first modified input data word, having (k+m) bits, by combining an input data word, having n bits, with an initialization value.