Patent Assignment
Reel/Frame 031334/0449
Assignment of Assignor's Interest
Recorded: 2013-09-19
Received: 2013-09-19
Pages: 23
Assignor
NXP B. V.
Executed: 2012-09-07
Assignee
PARTNERS FOR CORPORATE RESEARCH INTERNATIONAL
CLIFTON HOUSE, 75 FORT STREET, P.O. BOX 1350, GEORGE TOWN GRAND CAYMAN, KYX, KY1-1108, CAYMAN ISLANDS
Covered Properties
(92)
Method for Parallel Data Integrity Checking of Pci Express Devices
Application:
11/917,106 →
Esd Protection
Application:
12/663,822 →
Edge Rate Control for I2C Bus Applications
Application:
12/770,793 →
Simultaneous Control of Multiple I/O Banks in an I2C Slave Device
Application:
12/769,677 →
Programming Parallel I2C Slave Devices from a Single I2C Data Stream
Application:
12/761,662 →
Edge Rate Suppression for Open Drain Buses
Application:
12/630,453 →
Circuit Arrangement and Method for Supporting and Monitoring a Microcontroller
Application:
12/410,055 →
Oscillator Prescale Calibration for Harmonizing Multiple Devices with Independent Oscillators Over an I2C Bus Interface
Application:
12/269,018 →
Communications Device and Method for Configuring a Communication Port Depending on a Direction Condition of a Remote Device Communicatively Coupled to the Communications Port
Application:
10/592,190 →
Router, Network Comprising a Router, Method for Routing Data in a Network
Application:
11/817,323 →
Method and System for I2C Clock Generation
Application:
12/294,867 →
Memory Controller and Method for Coupling a Network and a Memory
Application:
11/917,020 →
Edge Rate Control for I2C Bus Applications
Application:
11/816,710 →
Region Protection Unit, Instruction Set and Method for Protecting a Memory Region
Application:
12/161,278 →
Two-Phase Data-Transfer Protocol
Application:
11/576,345 →
Esd Protected Integrated Capacitor with Large Capacity
Application:
11/817,706 →
Slave Bus Subscriber for a Serial Data Bus
Application:
11/577,704 →
Power Management for Buses in Cmos Circuits
Application:
12/066,113 →
Receiver for a Differential Data Bus
Application:
11/632,031 →
Method for Determining Cable Termination Resistances in Communication Networks and a Corresponding Communication Network
Application:
11/997,218 →
Asynchronous Data Buffer
Application:
11/996,312 →
Simulation Circuit of Pci Express Endpoint and Downstream Port for a Pci Express Switch
Application:
10/592,191 →
Memory Controller and Method for Coupling a Network and a Memory
Application:
11/917,018 →
Receiver with Adaptive Strobe Offset Adjustment
Application:
11/913,211 →
Device Identification Coding of Inter-Integrated Circuit Slave Devices
Application:
11/913,064 →
12C Slave Device with Programmable Write-Transaction Cycles
Application:
11/913,057 →
Dynamic 12C Slave Device Address Decoder
Application:
11/913,069 →
Simultaneous Control of Multiple I/O Banks in an 12C Slave Device
Application:
11/913,063 →
Slave Device with Latched Request for Service
Application:
11/913,061 →
Programming Parallel I2C Slave Devices from a Single I2C Data Stream
Application:
11/913,065 →
I2C Slave/Master Interface Enhancement Using State Machines
Application:
11/913,067 →
Switch Device and Communication Network Comprising Such Switch Device as Well as Method for Transmiting Data Within at Least One Virtual Channel
Application:
11/577,179 →
Ic Intrusion Detection
Application:
10/590,388 →
Performance Based Packet Ordering in a Pci Express Bus
Application:
11/719,532 →
Integrated Circuit with Input and/or Output Bolton Pads with Integrated Logic
Application:
11/576,142 →
Bus Connection Device
Application:
11/628,129 →
Digital Signal Processing Integrated Circuit with Io Connections
Application:
10/588,889 →
Circuit Arrangement and Method for Supporting and Monitoring a Microcontroller
Application:
10/569,185 →
Register File Gating to Reduce Microprocessor Power Dissipation
Application:
10/561,627 →
Signal Integrity Self-Test Architecture
Application:
10/557,679 →
Line Driver with Reduced Interference
Application:
10/556,250 →
Method of Monitoring the Communication in a Network
Application:
10/545,051 →
Arrangement for Compensation of Ground Offset in a Data Bus System
Application:
10/545,050 →
Electronic Circuit with Test Unit
Application:
10/520,198 →
Method for Effecting the Controlled Shutdown of Data Processing Units
Application:
10/514,850 →
Encapsulated Hardware Configuration/Control
Application:
10/538,458 →
Integrated Floating Power Transfer Device with Logic Level Control and Method
Application:
10/535,554 →
Interface Integrated Circuit Device for a Usb Connection
Application:
10/528,474 →
Method for Reducing Power Consumption in a State Retaining Circuit, State Retaining Circuit and Electronic Device
Application:
10/525,488 →
Bus System, Station for Use in a Bus System, and Bus Interface
Application:
10/517,513 →
Emulation of a Disconnect of a Device
Application:
10/919,756 →
Communication Bus System Operable in a Sleep Mode and a Normal Mode
Application:
10/499,401 →
Wireless Peripheral Interface with Universal Serial Bus Port
Application:
10/498,304 →
Output Driver Comprising an Improved Control Circuit
Application:
10/496,481 →
Usb Host Protocol
Application:
10/850,327 →
Can Device Featuring Advanced Can Filtering and Message Acceptance
Application:
10/797,790 →
Distribution of Status Information from Several Virtual Output Queus Over a Plurality of Switch Cards of a Packet Switching Device
Application:
10/480,130 →
Data Processing System and Method
Application:
10/678,625 →
Differential Output Structure with Reduced Skew for a Single Input
Application:
10/678,937 →
Circuit with Interconnect Test Unit
Application:
10/621,002 →
Bus System and Bus Interface
Application:
10/253,260 →
Bus System with Line Control During the Low-Power Phase
Application:
10/221,718 →
Communications Network and Method of Controlling the Communication Network
Application:
10/236,179 →
Embedded Data Set Processing
Application:
10/227,363 →
Entropy Estimation and Decimation for Improving the Randomness of True Random Number Generation
Application:
10/224,992 →
Security Processor with Bus Configuration
Application:
10/183,716 →
Clock System for Multiple Component System
Application:
10/176,209 →
Differential Output Structure with Reduced Skew for a Single Input
Application:
10/125,963 →
Device for Processing Data by Means of a Plurality of Processors
Application:
10/120,682 →
I/O Circuit with Mixed Supply Voltage Capability
Application:
10/100,357 →
Line Driver with Current Source Output and High Immunity to Rf Signals
Application:
10/095,348 →
Transceiver with Means for Error Management
Application:
10/055,387 →
Bidirectional Repeater Using High and Low Threshold Detection
Application:
10/027,672 →
Method and Arrangement for Rapid Silicon Prototyping
Application:
10/016,731 →
Extension for the Advanced Microcontroller Bus Architecture (Amba)
Application:
10/022,380 →
Circuit Arrangement for Error Recognition of a Two-Wire Data Bus
Application:
09/998,052 →
High-Speed Interchip Interface Protocol
Application:
09/997,609 →
Line Driver for Supplying Symmetrical Output Signals to a Two-Wire Communication Bus
Application:
10/022,381 →
Parallel Data Communication Realignment of Data Sent in Multiple Groups
Application:
09/966,297 →
Activity Detection in a Star Node with a Plurality of Coupled Network Nodes
Application:
09/923,609 →
Universal Pecl/Lvds Output Structure
Application:
09/922,420 →
Station and Method for Operating a Can Communication Line
Application:
09/912,134 →
Cutting Fluid Composition
Application:
09/850,740 →
Generalized I2C Slave Transmitter/Receiver State Machine
Application:
09/895,921 →
Integrated Circuit with Flash Memory
Application:
09/891,428 →
Microcontroller with Memory Content Dependent Conditional Command Decoder for Accessing Different Memory Types
Application:
09/888,458 →
Network Comprising a Plurality of Network Nodes for Media Access Checks
Application:
09/868,376 →
Parallel Communication Based on Balanced Data-Bit Encoding
Application:
09/871,197 →
Automatic Upgradeable Uart Circuit Arrangement
Application:
09/870,917 →
Parallel Data Communication Having Multiple Sync Codes
Application:
09/871,117 →
Parallel Data Communication Consuming Low Power
Application:
09/871,160 →
Accelerated Graphics Port (Apg) Controller Supporting Fast Write Transactions
Application:
09/778,653 →