IP Library Granted Patent US 7,493,408
Granted Patent B2
US 7,493,408 · App. 10/850,327 · Granted Feb 17, 2009

USB host protocol

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Quick Facts
Patent No.
US 7,493,408
App. No.
10/850,327
Granted
Feb 17, 2009
Kind
B2
Abstract

A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically. When the first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint, data packets are read from only the first transfer descriptor, until such time as it is detected that all data packets from the first transfer descriptor have been transmitted, and thereafter data packets are read from the second transfer descriptor.

Claims (22)

1. A method of transferring bulk and control data from a first device to a second device, comprising:

forming data to be transferred into a plurality of transfer descriptors, each transfer descriptor comprising a transfer descriptor header and payload data, wherein each transfer descriptor header defines an endpoint to which the payload data is to be transmitted, and wherein the payload data comprises at least one packet;

storing the formed transfer descriptors in a buffer memory in the first device; and reading data from the memory in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically;

further comprising, when first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint:

setting respective flags in the first and second transfer descriptor headers to different values;

setting a register value to an initial value, which is equal to the value of the flag in the first transfer descriptor header;

determining when all data packets from the first transfer descriptor have been transmitted, and thereafter changing the register value to be equal to the value of the flag in the second transfer descriptor header; and

reading data packets from the first and second transfer descriptor only when the value of the respective flag therein is equal to the register value.

2. A method as claimed in claim 1 , wherein the buffer memory comprises first and second buffers, the method further comprising, when the first and second transfer descriptor headers define a common endpoint:

storing the first and second transfer descriptors in different ones of the first and second buffers.

3. A method as claimed in claim 1 , wherein the first device comprises a USB host controller.

4. A host controller, for use in a bus communication system, the host controller comprising:

a buffer memory, for storing data to be transferred in a plurality of transfer descriptors, each transfer descriptor comprising a transfer descriptor header and payload data, wherein each transfer descriptor header defines an endpoint to which the payload data is to be transmitted, and wherein the payload data comprises at least one packet; and

means for reading data from the buffer memory in packets for transfer to a second device, with packets being read from the transfer descriptors cyclically;

the host controller being adapted, when first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint:

to set respective flags in the first and second transfer descriptor headers to different values;

to set a register value to an initial value, which is equal to the value of the flag in the first transfer descriptor header;

to determine when all data packets from the first transfer descriptor have been transmitted, and thereafter to change the register value to be equal to the value of the flag in the second transfer descriptor header; and

to read data packets from the first and second transfer descriptor only when the value of the respective flag therein is equal to the register value.

5. A host controller as claimed in claim 4 , wherein the buffer memory comprises first and second buffers, the host controller being adapted, when the first and second transfer descriptor headers define a common endpoint:

to store the first and second transfer descriptors in different ones of the first and second buffers.

6. A host controller as claimed in claim 4 , comprising a USB host controller.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2014
From: PARTNERS FOR CORPORATE RESEARCH INTERNATIONAL
To: FUTURE LINK SYSTEMS
Reel/Frame 032399/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2013
From: NXP B. V.
To: PARTNERS FOR CORPORATE RESEARCH INTERNATIONAL
Reel/Frame 031334/0449 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2004
From: CHANG, YEOW; TJIA, JEROME; MOO, WENG
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 015364/0928 →