I2C Slave/master interface enhancement using state machines
View Patent ↗Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate enhanced slave/master interfacing on an I2C bus using state machines. The communications system includes a first and second state-machine responsive to the rising edge of the clock signal, and a third state-machine, distinctly operational from the first and second state-machine, responsive to the falling edge of the clock signal. One of the first state-machine and the second state-machine conform to write states of the communications protocol, and the other of the first state-machine and the second state-machine conform to read states of the communications protocol.
1. A data communications system, comprising:
an I2C serial data transfer bus comprising:
for implementing a communications protocol, a clock line providing a clock signal having cyclically repeating rising edges and falling edges; and
a serial data line; and
a slave device, comprising:
a first and second state-machine responsive to the rising edge of the clock signal; and
a third state-machine, distinctly operational from the first and second state-machine, responsive to the falling edge of the clock signal;
wherein one of the first state-machine and the second state-machine conform to write states of the communications protocol, and the other of the first state-machine and the second state-machine conform to read states of the communications protocol.
2. The data communications system of claim 1 , wherein the first and second state-machines reset asynchronously on an I2C STOP condition or an I2C RESET or a START condition.
3. The data communications system of claim 1 , wherein the first and second state-machine transfer operational control of the slave device to the third state-machine under pre-determined conditions.
4. The data communications system of claim 1 , wherein the first and second state-machine runs in the foreground, assuming operational control of the slave device until transferring operational control of the slave device to the third state-machine.
5. The data communications system of claim 4 , wherein the third state-machine is configured to implement a slave device identification protocol in response to a device identification request by a master device when the third state-machine has operational control of the slave device.
6. The data communications system of claim 4 , wherein the third state-machine is configured to implement a loading of data, in parallel with other slave devices, in response to an ALL CALL request by a master device when the third state-machine has operational control of the slave device.
7. The data communications system of claim 4 , wherein the third state-machine is configured to implement an alert protocol in response to an SMBus Alert request by a master device when the third state-machine has operational control of the slave device.
8. In a communications system using an I2C serial data transfer bus that has a serial data line and a clock line used to implement a communications protocol, a method for a slave device to interface with a master device, the method comprising:
running a first and second state-machine in the slave device responsive to the rising edge of a clock signal provided on the clock line of the I2C serial data transfer bus; and
running a third state-machine in the slave device, distinctly operational from the first and second state-machine, responsive to the falling edge of the clock signal;
wherein one of the first and second state-machine conform to write states of the communications protocol, and the other of the first and second state-machine conform to read states of the communications protocol.
9. The method of claim 8 , comprising resetting the first and third state-machines asynchronously on an I2C STOP condition or an I2C RESET conditionor an I2C START condition.
10. The method of claim 8 , comprising transferring operational control of the slave device from the first and second state-machine to the third state-machine under pre-determined conditions.
11. The method of claim 10 , wherein running the third state-machine comprises implementing a slave device identification protocol in response to a device identification request by a master device when the third state-machine has operational control of the slave device.
12. The method of claim 10 , wherein running the third state-machine comprises implementing a loading of data, in parallel with other slave devices, in response to an ALL CALL request by a master device when the third state-machine has operational control of the slave device.
13. The method of claim 10 , wherein running the third state-machine comprises implementing an alert protocol in response to an SMBus Alert request by a master device when the third state-machine has operational control of the slave device.
14. The method of claim 8 , wherein running the first and second state-machine in the slave device comprises running the first and second state-machine in the foreground, thereby assuming operational control of the slave device until transferring operational control of the slave device to the third state-machine.
15. A data communications system, comprising:
means for running a first and second state-machine in the slave device responsive to the rising edge of a clock signal provided on the clock line of the I2C serial data transfer bus; and
means for running a third state-machine in the slave device, distinctly operational from the first and second state-machine, responsive to the falling edge of the clock signal;
wherein one of the first and second state-machine and the third state-machine conform to write states of the communications protocol, and the other of the first and second state-machine and the third state-machine conform to read states of the communications protocol.
16. The system of claim 15 , comprising means for transferring operational control of the slave device from the first and second state-machine to the third state-machine under pre-determined conditions.
17. The system of claim 15 , comprising means for gating the clock signal, wherein the first and second state-machine comprises an idle state such that the gated clock signal is not received by the first and second state-machine when the first and second state-machine are in their idle state.
18. The system of claim 15 , comprising means for gating the clock signal, wherein the third state-machine comprises an idle state such that the gated clock signal is not received by the third state-machine when the third state-machine is in its idle state.
19. The system of claim 15 , comprising means for implementing a slave device identification protocol in response to a device identification request by a master device.
20. The system of claim 15 , comprising means for implementing a loading of data, in parallel with other slave devices, in response to an ALL CALL request by a master device.