IP Library Granted Patent US 7,733,142
Granted Patent B2
US 7,733,142 · App. 11/816,710 · Granted Jun 8, 2010

Edge rate control for 1

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Quick Facts
Patent No.
US 7,733,142
App. No.
11/816,710
Granted
Jun 8, 2010
Kind
B2
Abstract

Consistent with an example embodiment, an edge-rate control circuit arrangement ( 300 ) for an I 2 C bus application comprises a first circuit stage ( 10 , M 1 , M 3 ), responsive to a state transition of a received signal. A second circuit stage ( 310, 25, 20, 35, 45 , M 4 , ESD) is responsive to the state transition of the received signal and includes drive circuitry (M 4 ) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I 2 C bus, and regulation circuitry ( 310 , R 1 , R 2 , M 0 , M 2 ) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I 2 C bus.

Claims (42)

1. An edge-rate control circuit arrangement for an I 2 C bus application, the arrangement comprising:

a first circuit stage, responsive to a state transition of a received signal; and

a second circuit stage responsive to the state transition of the received signal, the second circuit stage comprising:

drive circuitry that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I 2 C bus,

regulation circuitry that controls the drive circuitry and regulates a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I 2 C bus, wherein the regulation circuitry comprises:

a current-shunt circuit that provides a consistent response to the state transition of the received signal by shunting excess current away from the drive circuitry, the current-shunt circuit including a voltage-divider circuit and a current switch circuit that is activated in response to a voltage change present at a node in the voltage-divider circuit.

2. The edge-rate control circuit arrangement of claim 1 , wherein the regulation circuitry is responsive to a feedback signal which is in turn coupled to an output of the drive circuitry.

3. The edge-rate control circuit arrangement of claim 1 , wherein the drive circuitry is connected to the I 2 C bus.

4. The edge-rate control circuit arrangement of claim 1 , wherein the drive circuit and the regulation circuitry share at least one circuit node.

5. The edge-rate control circuit arrangement of claim 1 , wherein the regulation circuitry provides the transition rate for the edge-transition signal as a function of circuit parameters of the second circuit stage and independent of loading parameters due to the I 2 C bus.

6. The edge-rate control circuit arrangement of claim 1 , wherein the regulation circuitry provides the transition rate for the edge-transition signal as a function of circuit parameters of the second circuit stage and independent of parameters of circuit elements external to the second circuit stage.

7. The edge-rate control circuit arrangement of claim 1 , wherein the regulation circuitry provides the transition rate for the edge-transition signal as a function of circuit parameters of the second circuit stage and independent of voltage and current variations in a power supply level provided from a power node feeding power to the second circuit stage.

8. The edge-rate control circuit arrangement of claim 1 , wherein the regulation circuitry is responsive to a feedback signal which is in turn coupled to an output of the drive circuitry, and the feedback signal is coupled to the current-shunt circuit to facilitate regulation of the transition rate for the edge-transition signal.

9. The edge-rate control circuit arrangement of claim 1 , wherein the second circuit stage comprises:

an RC-based circuit that provides a fast response to the state transition of the received signal in order to activate the drive circuitry.

10. The edge-rate control circuit arrangement of claim 1 , wherein the I 2 C bus has at least two wires and provides passive communication by permitting signaling via active pull down and passive pull up.

11. The edge-rate control circuit arrangement of claim 1 , wherein the I 2 C bus has at least two wires and provides passive communication by permitting signaling via passive pull up.

12. The edge-rate control circuit arrangement of claim 1 , further including the I 2 C bus and at least one additional circuit including circuits corresponding to the said first and second circuit stages.

13. An edge-rate control circuit arrangement for a serial-communication bus application, the arrangement comprising:

first means for responding to a state transition of a received signal; and

second means for responding to the state transition of the received signal, the second means comprising:

means for activating in response to the state transition of the received signal in order to provide an edge-transition signal for the serial-communication bus, and

means for controlling the means for activating, said control 1 ing including regulation of a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the serial-communication bus, wherein the means for controlling comprises:

means for providing a consistent response to the state transition of the received signal by shunting excess current away from the drive circuitry, the means for providing including a voltage-divider circuit and a current switch circuit that is activated in response to a voltage change present at a node in the voltage-divider circuit.

14. The edge-rate control circuit arrangement of claim 13 , wherein the serial-communication bus is an I 2 C bus.

15. A method of edge-rate control for an I 2 C bus, the method comprising:

responding, with a first circuit stage, to a state transition of a received signal; and

responding, with a second circuit stage, to the state transition of the received signal;

activating a drive circuitry in response to the state transition of the received signal to provide an edge-transition signal for the I 2 C bus;

regulating the drive circuitry, with a regulation circuitry, to regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I 2 C bus;

providing, by an operation of a current-shunt circuit, a consistent response to the state transition of the received signal by shunting excess current away from the drive circuitry; and

activating, inside the current-shunt circuit, a current switch circuit in response to a voltage change present at a node in a voltage-divider circuit.

16. The method of claim 15 , further comprising:

responding, with the regulation circuitry, to a feedback signal that is coupled to an output of the drive circuitry.

17. The method of claim 15 , further comprising:

providing, with the regulation circuitry, the transition rate for the edge-transition signal as a function of circuit parameters of the second circuit stage and independent of loading parameters due to the I 2 C bus.

18. The method of claim 15 , further comprising:

providing, with the regulation circuitry, the transition rate for the edge-transition signal as a function of circuit parameters of the second circuit stage and independent of parameters of circuit elements external to the second circuit stage.

19. The method of claim 15 , further comprising:

providing, with the regulation circuitry, the transition rate for the edge-transition signal as a function of circuit parameters of the second circuit stage and independent of voltage and current variations in a power supply level provided from a power node feeding power to the second circuit stage.

20. The method of claim 15 , further comprising:

responding, with the regulation circuitry, to a feedback signal that is coupled to an output of the drive circuitry and to the current-shunt circuit to facilitate regulation of the transition rate for the edge-transition signal.

Assignments (13)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2014
From: PARTNERS FOR CORPORATE RESEARCH INTERNATIONAL
To: FUTURE LINK SYSTEMS
Reel/Frame 032399/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2013
From: NXP B. V.
To: PARTNERS FOR CORPORATE RESEARCH INTERNATIONAL
Reel/Frame 031334/0449 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2008
From: ANDERSON, ALMA; RUTKOWSKI, JOSEPH; OEHLER, DAVE
To: NXP B.V.
Reel/Frame 021550/0513 →