IP Library Granted Patent US 7,080,192
Granted Patent B1
US 7,080,192 · App. 10/678,885 · Granted Jul 18, 2006

File storage and erasure in flash memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,080,192
App. No.
10/678,885
Granted
Jul 18, 2006
Kind
B1
Abstract

A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last sector that stores part of the data block. For an operation erasing one or more data blocks, data blocks to be saved are read from an array and stored temporarily in a storage device. The entire array is then erased, after which the saved data blocks are rewritten in the memory with the amount of storage originally allocated to the erased data now being available for new data. This data arrangement does not subject any memory cells to a large accumulated cell disturbance because all data is read from the array and freshly re-written back into the array every time a record operation occurs. Additionally, the separate sectors in the memory device do not have different endurance histories that must be accounted for to extend the life of the memory. A single erase count for an array can be used in selection of operating parameters such as voltages used during accesses of memory cells in the array.

Claims (35)

1. A method for operating a semiconductor memory, comprising:

storing at least a portion of each of a plurality of data blocks in a physical array in the memory;

selecting one or more of the data blocks for erasure;

reading first data from the physical array, wherein the first data comprises all data from blocks other than the data blocks selected for erasure;

erasing the entire physical array, wherein erasing begins after reading the first data; and

writing the first data back into the physical array after erasing the entire physical array.

2. The method of claim 1 , further comprising storing the first data in temporary storage while erasing the physical array, wherein the temporary storage is external to the semiconductor memory.

3. The method of claim 1 , wherein erasing the physical array comprises simultaneously erasing all memory cells in the physical array.

4. The method of claim 1 , wherein the physical array is partitioned into a plurality of separately erasable sectors, and erasing the entire physical array comprises erasing all of the sectors.

5. The method of claim 4 , wherein the sectors are sequentially erased.

6. The method of claim 4 , wherein the writing comprises writing data from different data blocks at consecutive addresses in the physical array, without regard for boundaries between sectors.

7. The method of claim 1 , wherein further comprises writing data from one or more new data blocks into the erased physical array.

8. The method of claim 1 , wherein the memory is a Flash memory.

9. The method of claim 1 , wherein the physical array contains multi-bit-per-cell memory cells.

10. The method of claim 1 , wherein reading data from at least a portion of the physical array, comprises reading all data stored in the physical array, including second data that is the one or more data blocks selected for erasure.

11. The method of claim 1 , further comprising:

maintaining a count indicating a number of erase operations performed on the physical array; and

selecting parameters for operation of the physical array, the parameters being selected according to the count.

12. A system for storage of data blocks, comprising:

a first memory that is a non-volatile semiconductor memory; and

a computer system connected to the first memory, the computer system comprising a storage device, and a processor that executes file management procedure, wherein execution of the file management procedure comprises:

identifying a plurality of data blocks at least partly stored in an array in the first memory;

selecting one or more of the data blocks for erasure;

reading from the array data corresponding to all of the data blocks that are not selected for erasure;

storing in the storage device, the data read from the array;

erasing the array in entirety; and

writing into the first memory, the data from the storage device.

13. The system of claim 12 , wherein the data blocks are files representing music, and the first memory is a memory of a player of the music.

14. The system of claim 13 , wherein the computer system is a personal computer.

15. The system of claim 12 , wherein the file management procedure writes the data blocks from the storage device into the erased array.

16. The system of claim 15 , wherein the file management procedure further comprises writing new data into the erased array.

17. The system of claim 12 , wherein erasing the array comprises simultaneously erasing all memory cells in the array.

18. The system of claim 12 , wherein the array is partitioned into a plurality of separately erasable sectors, and erasing the array comprises erasing all of the sectors.

19. The system of claim 18 , wherein the sectors are sequentially erased.

20. The system of claim 18 , wherein the writing comprises writing data from different data blocks at consecutive addresses in the array, without regard for boundaries between sectors.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2006
From: INTERNATIONAL DEVELOPMENT AND LICENSING
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 017230/0319 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2005
From: MULTI LEVEL MEMORY TECHNOLOGY
To: INTERNATIONAL DEVELOPMENT AND LICENSING
Reel/Frame 017176/0517 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2005
From: MULTI LEVEL MEMORY TECHNOLOGY (CALIFORNIA)
To: MULTI LEVEL MEMORY TECHNOLOGY (NEVADA)
Reel/Frame 016800/0640 →