IP Library Granted Patent US 7,726,013
Granted Patent B2
US 7,726,013 · App. 10/680,173 · Granted Jun 1, 2010

Method of manufacturing circuit board including transfer chip having a plurality of first pad electrodes connected to wiring

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 7,726,013
App. No.
10/680,173
Granted
Jun 1, 2010
Kind
B2
Abstract

A circuit board manufacturing method, including forming a transfer chip, the forming of the transfer chip including, forming a wiring above a first substrate, forming a plurality of first pad electrodes so as to be connected to the wiring and so as to be included in the transfer chip, and joining the transfer chip with a member such that the plurality of first pad electrodes contact the member.

Claims (17)

1. A circuit board manufacturing method, comprising:

forming a transfer chip on and above a first substrate, the transfer chip having (1) a bottom adjacent the first substrate, (2) a thin-film electrical circuit formed of stacked films above the first substrate and the bottom and (3) a plurality of transfer chip pad electrodes formed above the stacked films, the pad electrodes including a first pad electrode having a first top positioned at a highest level within the first pad electrode and a second pad electrode having a second top positioned at a highest level within the second pad electrode, the first pad electrode having a first height measured from the bottom of the transfer chip to the first top of the first pad electrode, and the second pad electrode having a second height measured from the bottom of the transfer chip to the second top of the second pad electrode;

forming a transfer region on a second substrate, the transfer region having (1) electrical circuit wiring and (2) a plurality of transfer region pad electrodes connected to the electrical circuit wiring;

adjusting at least one of the first height and the second height by adding at least one height adjusting film so that the first height becomes substantially the same as the second height; and

joining the transfer chip to the transfer region on the second substrate, such that the thin-film electrical circuit is electrically connected to the electrical circuit wiring via contact between respective ones of the transfer chip pad electrodes and the transfer region pad electrodes.

2. The circuit board manufacturing method according to claim 1 ,

the plurality of transfer region pad electrodes including a third pad electrode and a fourth pad electrode,

the joining of the transfer chip being carried out such that the first pad electrode contacts the third pad electrode.

3. The circuit board manufacturing method according to claim 2 ,

the joining of the transfer chip being carried out such that the second pad electrode contacts the fourth pad electrode.

4. The circuit board manufacturing method according to claim 1 ,

the plurality of transfer region pad electrodes including (1) a third pad electrode that has a third top positioned at a highest level within the third pad electrode, the third pad electrode having a third height measured from a bottom of the transfer region to the third top, and (2) a fourth pad electrode that has a fourth top positioned at a highest level within the fourth pad electrode, the fourth pad electrode having a fourth height measured from the bottom of the transfer region to the fourth top, and

the third height and the fourth height being different from each other.

5. The circuit board manufacturing method according to claim 4 ,

wherein the first height of the first pad electrode is adjusted by a first amount and the second height of the second pad electrode is adjusted by a second amount, and

the joining of the transfer chip being carried out such that the first pad electrode and the second pad electrode contact the third pad electrode and the fourth pad electrode, respectively,

the first amount and the second amount being selected such that, after joining, the transfer chip and the transfer region maintain a common horizontal level.

Assignments (3)
MERGER Recorded Aug 7, 2012
From: SAMSUNG LED CO., LTD.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 028744/0272 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2012
From: SEIKO EPSON CORPORATION
To: SAMSUNG LED CO., LTD.
Reel/Frame 027524/0837 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2004
From: KIMURA, MUTSUMI
To: SEIKO EPSON CORPORATION
Reel/Frame 014406/0443 →
Priority Claims (1)
JP 2002-295134 · Oct 8, 2002 · national
Continuity (1)
Related Publication 20040128829A1 · Jul 8, 2004