Multi-Pair Gigabit Ethernet Transceiver having decision feedback equalizer
View Patent ↗Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
1. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:
a decoder circuit for receiving and decoding at least one intersymbol interference (ISI) compensated signal sample, and generating tentative decisions and a final decision; and
a decision feedback equalizer coupled in feedback fashion to the decoder circuit, the decision feedback equalizer including a set of low-ordered coefficients and a set of high-ordered coefficients, the decision feedback equalizer generating a first portion of ISI compensation based on the tentative decisions and the high-ordered coefficients; and
a convolution engine coupled to the decision feedback equalizer to receive values of the low-ordered coefficients, the convolution engine computing a set of pre-computed values representing a set of potential second ISI compensation portions.
2. The integrated circuit communication device according to claim 1 , wherein a first digital signal is combined with the first portion of ISI compensation to produce a second digital signal partially compensated for ISI.
3. The integrated circuit communication device according to claim 2 , further comprising a multiple decision feedback equalizer coupled to the decision feedback equalizer and the convolution engine, the multiple decision feedback equalizer combining the set of pre-computed values with the second digital signal to produce a set of potential digital signals, one of the potential digital signals being substantially compensated for ISI.
4. The integrated circuit communication device according to claim 3 , wherein the decision feedback equalizer compensates for ISI introduced by transmission channel characteristics.