Multiple leadframe laminated IC package
View Patent ↗A method of fabricating an integrated circuit package. The method includes providing a first leadframe and a second leadframe, laminating the second leadframe to a portion of the first leadframe in order to create a multi-layer laminated leadframe, and mounting a semiconductor die on another portion of the first leadframe.
1. An integrated circuit package comprising:
a first leadframe;
a second leadframe laminated to a portion of said first leadframe thereby providing a multi-layer laminated leadframe;
a semiconductor die having opposing first and second surfaces, the first surface of said semiconductor die being mounted to another portion of said first leadframe; and
a third lead frame laminated to at least a portion of said second surface of said semiconductor die.
2. The integrated circuit package according to claim 1 , wherein said first leadframe comprises a copper strip having silver plating on the second side and said second leadframe is soldered to the first side of the first leadframe.
3. The integrated circuit package according to claim 1 , wherein said second leadframe comprises a copper strip having solder plating on one surface and being soldered to said first leadframe on an opposing second surface thereof.
4. The integrated circuit package according to claim 1 , wherein said third leadframe comprises a copper strip having a solder plating on one surface and being soldered to said first leadframe on an opposing second surface thereof.
5. The integrated circuit package according to claim 1 wherein said semiconductor die is coated with at least one of titanium, tungsten, gold, or a combination thereof for soldering.