Methods of forming power semiconductor devices using boule-grown silicon carbide drift layers and power semiconductor devices formed thereby
View Patent ↗Methods of forming high voltage silicon carbide power devices utilize high purity silicon carbide drift layers that are derived from high purity silicon carbide wafer material, instead of prohibitively costly epitaxially grown silicon carbide layers. The methods include forming both minority carrier and majority carrier power devices that can support greater than 10 kV blocking voltages, using drift layers having thicknesses greater than about 100 um. The drift layers are formed as boule-grown silicon carbide drift layers having a net n-type dopant concentration therein that is less than about 2×10 15 cm −3 . These n-type dopant concentrations can be achieved using neutron transmutation doping (NTD) techniques.
1. A method of forming a silicon carbide MOSFET device having a 10 kV or higher blocking voltage rating, comprising the steps of:
forming a silicon carbide boule using a seeded sublimation growth technique or a high-temperature CVD growth technique;
irradiating the silicon carbide boule with thermal neutrons of sufficient fluence to thereby transmute some fraction of silicon atoms to phosphorus atoms within the silicon carbide boule;
forming a silicon carbide wafer from the irradiated silicon carbide boule;
forming a boule-grown silicon carbide drift layer having a net n-type dopant concentration therein that is less than about 2×10 15 cm −3 by annealing the silicon carbide wafer at a sufficient temperature to reduce a trap density therein;
forming a p-type silicon carbide base region on the silicon carbide drift layer;
forming an n-type silicon carbide source region that defines a p-n rectifying junction with the p-type silicon carbide base region; and
forming a gate electrode on the p-type silicon carbide base region.
2. The method of claim 1 , wherein the silicon carbide drift layer has a thickness in a range from between about 100 μm and about 400 μm.
3. A method of forming a high-voltage silicon carbide device, comprising the steps of:
forming a silicon carbide boule using a seeded sublimation growth technique or a high-temperature CVD growth technique;
irradiating the silicon carbide boule with thermal neutrons of sufficient fluence to thereby transmute some fraction of silicon atoms to phosphorus atoms within the silicon carbide boule;
forming a silicon carbide wafer from the irradiated silicon carbide boule;
forming a boule-grown silicon carbide drift layer having a net n-type dopant concentration therein that is less than about 2×10 15 cm −3 by annealing the silicon carbide wafer at a sufficient temperature to achieve a characteristic minority carrier lifetime in excess of 50 nanoseconds therein; and
forming n-type and p-type silicon carbide layers on the silicon carbide drift layer.
4. The method of claim 3 , wherein the silicon carbide drift layer has a thickness in a range from between about 100 μm and about 400 μm.
5. A method of forming a silicon carbide JFET having a 10 kV or higher blocking voltage rating, comprising the steps of:
forming a boule-grown silicon carbide drift layer having a net n-type dopant concentration therein that is less than about 2×10 15 cm −3 ;
forming an n-type silicon carbide epilayer on the silicon carbide drift layer;
forming an n-type silicon carbide source region in the n-type silicon carbide epilayer; and
forming a p-type silicon carbide gate electrode on the n-type silicon carbide epilayer;
wherein said step of forming an n-type silicon carbide epilayer is preceded by the step of forming a p-type silicon carbide buried region in the silicon carbide drift layer;
wherein said step of forming an n-type silicon carbide epilayer comprises forming an n-type silicon carbide epilayer that defines a p-n rectifying junction with the p-type silicon carbide buried region and a non-rectifying junction with the silicon carbide drift layer; and
wherein said step of forming a p-type silicon carbide gate electrode comprises forming a p-type silicon carbide gate electrode that extends opposite a portion of the p-type silicon carbide buried region.
6. The method of claim 5 , further comprising the step of forming a source electrode that ohmically contacts the n-type silicon carbide source region and the p-type silicon carbide buried region.
7. The method of claim 5 , wherein said step of forming a boule-grown silicon carbide drift layer comprises annealing a boule-grown silicon carbide wafer at a sufficiently high temperature to reduce a density of traps therein.
8. A method of forming a silicon carbide JFET having a 10 kV or higher blocking voltage rating, comprising the steps of:
forming a silicon carbide boule using a seeded sublimation growth technique;
irradiating the silicon carbide boule with thermal neutrons of sufficient fluence to thereby transmute silicon atoms to phosphorus atoms within the silicon carbide boule;
forming a silicon carbide drift layer having a net n-type dopant concentration therein that is less than about 2×10 15 cm −3 from the irradiated silicon carbide boule;
forming an n-type silicon carbide epilayer on the silicon carbide drift layer;
forming an n-type silicon carbide source region in the n-type silicon carbide epilayer; and
forming a p-type silicon carbide gate electrode on the n-type silicon carbide epilayer.
9. The method of claim 8 , wherein the silicon carbide drift layer has a thickness in a range from between about 100 μm and about 400 μm.
10. A method of forming a silicon carbide MOSFET device having a 10 kV or higher blocking voltage rating, comprising the steps of:
forming a silicon carbide boule using a seeded sublimation growth technique;
irradiating the silicon carbide boule with thermal neutrons of sufficient fluence to thereby transmute some fraction of silicon atoms to phosphorus atoms within the silicon carbide boule;
forming a silicon carbide drift layer having a net first conductivity type dopant concentration therein that is less than about 2×10 15 cm −3 from the irradiated silicon carbide boule;
forming a second conductivity type silicon carbide base region on the silicon carbide drift layer;
forming a first conductivity type silicon carbide source region that defines a p-n rectifying junction with the second conductivity type silicon carbide base region; and
forming a gate electrode on the second conductivity type silicon carbide base region.
11. The method of claim 10 , wherein the silicon carbide drift layer has a thickness in a range from between about 100 μm and about 400 μm.
12. A method of forming a high-voltage silicon carbide device, comprising the steps of:
forming a silicon carbide boule using a seeded sublimation growth technique or a high-temperature CVD growth technique;
irradiating the silicon carbide boule with thermal neutrons of sufficient fluence to thereby transmute some fraction of silicon atoms to phosphorus atoms within the silicon carbide boule;
forming a silicon carbide wafer from the irradiated silicon carbide boule; and
forming a boule-grown silicon carbide drift layer having a net n-type dopant concentration therein that is less than about 2×10 15 cm −3 by annealing the silicon carbide wafer at a sufficient temperature to achieve a characteristic minority carrier lifetime in excess of 50 nanoseconds therein.
13. The method of claim 12 , wherein the silicon carbide wafer layer has a thickness in a range from between about 100 μm and about 400 μm.