Patent Assignment
Reel/Frame 072989/0001
Release of Security Interest in Intellectual Property Collateral at Reel/Frame No. 64185/0755
Recorded: 2025-09-30
Pages: 67
Assignor
U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Executed: 2025-09-29
Assignee
WOLFSPEED, INC.
4600 SILICON DRIVE, DURHAM, NORTH CAROLINA, 27703
Covered Properties
(754)
Wide bandgap transistors with gate-source field plates
Igbt Structure for Wide Band-Gap Semiconductor Materials
Application:
14/212,991 →
Publication:
US US20150263145A1
Semiconductors Having Die Pads with Environmental Protection and Process of Making Semiconductors Having Die Pads with Environmental Protection
Application:
16/704,644 →
Publication:
US US20210175138A1
Methods and Systems for Matching Both Dynamic and Static Parameters in Dies, Discretes, and/or Modules, and Methods and Systems Based on the Same
Nondestructive Characterization for Crystalline Wafers
High Speed, Efficient Sic Power Module
Semiconductor Die Having a Drift Region with a Charge Compensation Region Formed Therein Where the Charge Compensation Region Has a Plurality of Guard Rings Formed in First and Second Opposite Doping Type Portions
Application:
16/806,489 →
Publication:
US US20210273090A1
Power Semiconductor Package with Improved Performance
High Speed, Efficient Sic Power Module
Semiconductor Device Having a First Barrier Layer Formed on a Gate Pad and Gate Electrode and an Isolation Layer Provided Between the First Barrier Layer and a Second Barrier Layer Formed Thereon
Application:
16/863,642 →
Publication:
US US20210343847A1
Conduction Enhancement Layers for Electrical Contact Regions in Power Devices
Group III-Nitride High-Electron Mobility Transistors Configured with Recessed Source and/or Drain Contacts for Reduced On State Resistance and Process for Implementing the Same
Application:
16/876,752 →
Publication:
US US20210359118A1
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Power Devices with a Hybrid Gate Structure
Laser-Assisted Method for Parting Crystalline Material
Power Module
Shielding Arrangements for Transformer Structures
Application:
16/942,082 →
Publication:
US US20220037080A1
Sidewall Dopant Shielding Methods and Approaches for Trenched Semiconductor Device Structures
Power Silicon Carbide Based Semiconductor Devices with Improved Short Circuit Capabilities and Methods of Making Such Devices
Packaging for Rf Transistor Amplifiers
Electronic Device Packages with Internal Moisture Barriers
Vertical Power Transistor Device
Patent:
49,913 →
Application:
17/080,062 →
Packaged Transistor Having Die Attach Materials with Channels and Process of Implementing the Same
Transistor Packages with Improved Die Attach
Protection Structures for Semiconductor Devices with Sensor Arrangements
Passivation Structures for Semiconductor Devices Having Patterned Structures Over Edge Termination Regions
Application:
17/088,686 →
Publication:
US US20220140132A1
Power Semiconductor Devices with Improved Overcoat Adhesion and/or Protection
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
Semiconductor Devices Including an Offset Metal to Polysilicon Gate Contact
Application:
17/096,147 →
Publication:
US US20220149165A1
Packaged Rf Power Device with Pcb Routing Outside Protective Member
Methods and Apparatuses Related to Shaping Wafers Fabricated by Ion Implantation
Application:
16/950,414 →
Publication:
US US20210066081A1
Power Semiconductor Devices Having Gate Trenches and Buried Edge Terminations and Related Methods
Methods and Systems for Component Analysis, Sorting, and Sequencing Based on Component Parameters and Devices Utilizing the Methods and Systems
Finfet Power Semiconductor Devices
Power Transistor with Soft Recovery Body Diode
Large Dimension Silicon Carbide Single Crystalline Materials with Reduced Crystallographic Stress
Group III-Nitride High-Electron Mobility Transistors with Buried P-Type Layers and Process for Making the Same
Large Diameter Silicon Carbide Wafers
Process, System, and Device for Determining a Related Product
Application:
17/138,193 →
Publication:
US US20220207464A1
Radio Frequency Transistor Amplifiers Having Widened and/or Asymmetric Source/Drain Regions for Improved on-Resistance Performance
Devices Incorporating Stacked Bonds and Methods of Forming the Same
Packaged Electronic Devices Having Dielectric Substrates with Thermally Conductive Adhesive Layers
Group Iii-Nitride High-Electron Mobility Transistors with Gate Connected Buried P-Type Layers and Process for Making the Same
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
Power Semiconductor Device with Reduced Strain
Wide Bandgap Semiconductor Device with Sensor Element
Power Component Configured for Improving Partial Discharge Performance and System and Process of Implementing the Same
Power Transistor with Soft Recovery Body Diode
Carrier-Assisted Method for Parting Crystalline Material Along Laser Damage Region
Power Module Having Electrical Interconnections Using Mechanical Fittings and Process of Implementing the Same
Package with Different Types of Semiconductor Dies Attached to a Flange
Power Module
Power Module
Patent:
1,073,632 →
Application:
29/780,368 →
Group Iii-Nitride Transistors with Back Barrier Structures and Buried P-Type Layers and Methods Thereof
Circuits and Group Iii-Nitride Transistors with Buried P-Layers and Controlled Gate Voltages and Methods Thereof
Circuits and Group Iii-Nitride High-Electron Mobility Transistors with Buried P-Type Layers Improving Overload Recovery and Process for Implementing the Same
Field Effect Transistor with Source-Connected Field Plate
Field Effect Transistor with Selective Modified Access Regions
Field Effect Transistors with Modified Access Regions
Field Effect Transistor with Selective Channel Layer Doping
Multilayer Encapsulation for Humidity Robustness and Related Fabrication Methods
Device and Process for Fault Detection of a Power Device
Reduced Optical Absorption for Silicon Carbide Crystalline Materials
Package for Power Electronics
Power Semiconductor Die Having a Combination of Active Area and Termination Region Area Being Less Than 90% of Total Die Area
Application:
17/357,103 →
Publication:
US US20220416077A1
Superjunction Power Semiconductor Devices Formed via Ion Implantation Channeling Techniques and Related Methods
Semiconductor Devices Having Asymmetric Integrated Gate Resistors for Balanced Turn-on/Turn-Off Behavior
Power Semiconductor Devices Including Angled Gate Trenches
Encapsulation Stack for Improved Humidity Performance and Related Fabrication Methods
Interconnect Metal Openings Through Dielectric Films
Arrangements of Power Semiconductor Devices for Improved Thermal Performance
Semiconductor Device Incorporating a Substrate Recess
Vertical Power Devices Fabricated Using Implanted Methods
Contact and Die Attach Metallization for Silicon Carbide Based Devices and Related Methods of Sputtering Eutectic Alloys
Transistor Semiconductor Die with Increased Active Area
Transistor Device Structure with Angled Wire Bonds
Multiple Silicide Process for Separately Forming N-Type and P-Type Ohmic Contacts and Related Devices
Transistor with Ohmic Contacts
Compact Power Module
Packaged Semiconductor Devices, and Package Molds for Forming Packaged Semiconductor Devices
Edge Termination for Power Semiconductor Devices and Related Fabrication Methods
Group Iii-Nitride High-Electron Mobility Transistors with a Buried Metallic Conductive Material Layer and Process for Making the Same
Package for Power Electronics
Limiting Failures Caused by Dendrite Growth on Semiconductor Chips
Laser-Assisted Method for Parting Crystalline Material
Wide Bandgap Unipolar/Bipolar Transistor
Interface Layer Control Methods for Semiconductor Power Devices and Semiconductor Devices Formed Thereof
Multilayer Encapsulation for Humidity Robustness and Highly Accelerated Stress Tests and Related Fabrication Methods
Semiconductor Die Including a Metal Stack
Application:
17/665,191 →
Publication:
US US20230253359A1
Power Semiconductor Devices Having Multilayer Gate Dielectric Layers That Include an Etch Stop/Field Control Layer and Methods of Forming Such Devices
Methods of Forming Semiconductor Power Devices Having Graded Lateral Doping
Radio Frequency Transistor Amplifiers Having Self-Aligned Double Implanted Source/Drain Regions for Improved on-Resistance Performance and Related Methods
Semiconductor Packages with Increased Power Handling
Methods for Dicing Semiconductor Wafers Having a Metallization Layer and Semiconductor Devices Made by the Methods
Systems and Processes for Increasing Semiconductor Device Reliability
Support Shield Structures for Trenched Semiconductor Devices
Power Semiconductor Device with Shallow Conduction Region
Application:
17/705,172 →
Publication:
US US20230327026A1
Packaged Electronic Devices Having Transient Liquid Phase Solder Joints and Methods of Forming Same
Power Semiconductor Devices Including Multiple Gate Bond Pads
Die Backside Metallization Methods and Apparatus
Application:
17/658,691 →
Publication:
US US20230326897A1
Transistor Including a Discontinuous Barrier Layer
Dynamic Performance of on-Chip Current Sensors
Application:
17/736,720 →
Publication:
US US20230361212A1
Dual Inline Power Module
Group Iii Nitride-Based Monolithic Microwave Integrated Circuits Including Static Random Access Memory Blocks with Associated Addressing and Buffering Circuits
Vertical Power Devices Having Mesas and Etched Trenches Therebetween
Power Semiconductor Devices Having Moisture Barriers
Application:
17/747,128 →
Publication:
US US20230378010A1
Trench Bottom Shielding Methods and Approaches for Trenched Semiconductor Device Structures
High Power Transistor with Interior-Fed Fingers
Field Effect Transistor with Multiple Stepped Field Plate
Power Package Having Connected Components and Processes Implementing the Same
Application:
17/837,640 →
Publication:
US US20230402360A1
Semiconductor Devices Having Asymmetric Integrated Lumped Gate Resistors for Balanced Turn-on/Turn-Off Behavior and/or Multiple Spaced-Apart Lumped Gate Resistors for Improved Power Handling
Application:
17/843,010 →
Publication:
US US20230023195A1
Power Module
Gate Trench Power Semiconductor Devices Having Trench Shielding Patterns Formed During the Well Implant and Related Methods
Circuits and Methods for Controlling Bidirectional Cllc Converters
Gate Trench Power Semiconductor Devices Having Improved Breakdown Performance and Methods of Forming Such Devices
Semiconductor Devices Having on-Chip Gate Resistors
Semiconductor Device with Selectively Grown Field Oxide Layer in Edge Termination Region
Top Side Cooled Semiconductor Packages
Application:
17/849,316 →
Publication:
US US20230420329A1
Methods of Forming Ohmic Contacts on Semiconductor Devices with Trench/Mesa Structures
Packages with Backside Mounted Die and Exposed Die Interconnects and Methods of Fabricating the Same
Methods and Systems for Implementing a Modular Platform Implementing Active Devices
Application:
17/848,526 →
Publication:
US US20230422399A1
Methods of Forming Uniformly Doped Deep Implanted Regions in Silicon Carbide and Silicon Carbide Layers Including Uniformly Doped Implanted Regions
Application:
17/849,037 →
Publication:
US US20230420575A1
Semiconductor Device Packages with Exposed Heat Dissipating Surfaces and Methods of Fabricating the Same
Optimization of Power Module Performance via Parasitic Mutual Coupling
Gallium Nitride High-Electron Mobility Transistors with P-Type Layers and Process for Making the Same
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Multi-Cavity Package Having Single Metal Flange
Application:
17/867,801 →
Publication:
US US20220352141A1
Electronic Devices with Reduced Ohmic to Ohmic Dimensions
Application:
17/893,277 →
Publication:
US US20240072125A1
Semiconductor Package
Patent:
1,056,862 →
Application:
29/866,001 →
Transistor Die Including Matching Circuit
Application:
17/900,652 →
Publication:
US US20240072732A1
Vertical Semiconductor Device with Improved Ruggedness
Device and Process for Implementing Silicon Carbide (Sic) Surface Mount Devices
Transistor Package and Process of Implementing the Transistor Package
Barrier Structure for Dispersion Reduction in Transistor Devices
Barrier Structure for Sub-100 Nanometer Gate Length Devices
Application:
17/951,711 →
Publication:
US US20240105824A1
High Reliability Semiconductor Devices and Methods of Fabricating the Same
Application:
17/935,509 →
Publication:
US US20230019230A1
Power Module
Patent:
1,036,395 →
Application:
29/855,192 →
Silicon Carbide Device with Single Metallization Process for Ohmic and Schottky Contacts
Application:
17/957,737 →
Publication:
US US20240113235A1
Implanted Regions for Semiconductor Structures with Deep Buried Layers
Application:
17/961,032 →
Publication:
US US20240120202A1
Methods of Forming Semiconductor Structures and Resulting Semiconductor Structures
Application:
17/966,081 →
Publication:
US US20240128336A1
Semiconductor Devices with Additional Mesa Structures for Reduced Surface Roughness
Application:
17/977,003 →
Publication:
US US20240145537A1
Radio Frequency Power Amplifier Implementing an Off Mode Output Impedance Control and a Process of Implementing the Same
Core-Shell Particle Die-Attach Material
Application:
18/074,079 →
Publication:
US US20240182757A1
Multiple Transport Level Tester System
Transistor Devices Including Self-Aligned Ohmic Contacts and Contact Regions and Related Fabrication Methods
Application:
18/063,787 →
Publication:
US US20240194751A1
Power Electronics Package Layouts, Structures, and/or Configurations for One or More Power Devices and Processes Implementing the Same
Application:
18/145,502 →
Publication:
US US20240213124A1
Gate Trench Power Semiconductor Devices Having Self-Aligned Trench Shielding Regions and Related Methods
Application:
18/093,343 →
Publication:
US US20240234495A1
Buried Shield Structures for Power Semiconductor Devices and Related Fabrication Methods
Device Design for Short-Circuit Protection of Transistors
Semiconductor Device and Related Fabrication Method
Application:
18/152,130 →
Publication:
US US20240234370A1
Thermal Enhanced Power Semiconductor Package
Application:
18/154,353 →
Publication:
US US20240243031A1
Power Module Having an Elevated Power Plane with an Integrated Signal Board and Process of Implementing the Same
Power Semiconductor Devices Including Multiple Layer Metallization
Application:
18/160,765 →
Publication:
US US20240213196A1
Semiconductor Device Packages Including Multilayer Stacks with Improved Adhesion
Application:
18/161,144 →
Publication:
US US20240258217A1
Integrated Power Module
Edge Termination Structures for Semiconductor Devices
Flip-Chip Field Effect Transistor Layouts and Structures
Application:
18/105,586 →
Publication:
US US20240266348A1
Semiconductor Device Having Semiconductor Structure with Polarity Inverting Layer
Application:
18/164,205 →
Publication:
US US20240266419A1
Semiconductor Structure for Improved Radio Frequency Thermal Management
Application:
18/164,249 →
Publication:
US US20240266426A1
Power Semiconductor Devices Having Non-Rectangular Semiconductor Die for Enhanced Mechanical Robustness and Reduced Stress and Electric Field Concentrations
Application:
18/107,537 →
Publication:
US US20240274660A1
Hourglass-Shaped Vias for Group Iii-Nitride Semiconductor Devices
Application:
18/168,985 →
Publication:
US US20240274507A1
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
Electroless Die-Attach Process for Semiconductor Packaging
Application:
18/169,492 →
Publication:
US US20240274514A1
Metal Nitride Core-Shell Particle Die-Attach Material
Nitrogen-Polar Group III-Nitride Semiconductor Device with Isolation Implant Regions
Application:
18/173,534 →
Publication:
US US20240290876A1
Electric Field Modification for Nitrogen-Polar Group III-Nitride Semiconductor Devices
Application:
18/175,231 →
Publication:
US US20240290847A1
Field Reducing Structures for Nitrogen-Polar Group III-Nitride Semiconductor Devices
Power Semiconductor Package
Application:
18/179,036 →
Publication:
US US20240304507A1
Metal Stack with Phonon Scattering Layer That Forms a Non-Ohmic Contact to a Semiconductor Layer
Application:
18/121,782 →
Publication:
US US20240313099A1
High-Performance Stress Buffer Die-Coat and Devices and Processes Implementing the Same
Application:
18/187,924 →
Publication:
US US20240321663A1
Die-Coat Material Configured to Enhance Device Reliability and Devices and Processes Implementing the Same
Application:
18/187,804 →
Publication:
US US20240321659A1
Semiconductor Devices with Integrated Test Structures
Application:
18/125,610 →
Publication:
US US20240321651A1
Semiconductor Devices with Integrated Test Areas
Application:
18/125,655 →
Publication:
US US20240321647A1
Power Semiconductor Devices Including a Trenched Gate and Methods of Forming Such Devices
Power Module Having Pin Fins
Patent:
1,041,429 →
Application:
29/873,303 →
Silicon Carbide Thermal Bridge Integrated on a Low Thermal Conductivity Substrate and Processes Implementing the Same
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
Semiconductor Power Devices Having Multiple Gate Trenches and Methods of Forming Such Devices
Application:
18/302,843 →
Publication:
US US20230261073A1
Semiconductor Devices Having Gate Resistors with Low Variation in Resistance Values
Heteroepitaxial Semiconductor Devices with Enhanced Thermal Dissipation
Application:
18/137,797 →
Publication:
US US20240355918A1
Power Semiconductor Devices Including Beryllium Metallization
Application:
18/304,869 →
Publication:
US US20240355738A1
Signal Loop Busbars and Semiconductor Power Modules Including the Same and Processes of Implementing the Same
Application:
18/305,976 →
Publication:
US US20240356322A1
Semiconductor Devices with Low Barrier Height Schottky Contacts
Application:
18/138,240 →
Publication:
US US20240355897A1
Power Package
Patent:
1,121,577 →
Application:
29/875,226 →
Method for Reducing Parasitic Capacitance and Increasing Peak Transconductance While Maintaining on-State Resistance and Related Devices
Power Module
Patent:
1,134,247 →
Application:
29/875,793 →
Mosfets with Implanted Charge Compensation Regions
Application:
63/466,479 →
Semi-Insulating Gan and Method of Making the Same
Low 1C Screw Dislocation 3 Inch Silicon Carbide Wafer
Low Micropipe 100 Mm Silicon Carbide Wafer
Optically Triggered Wide Bandgap Bipolar Power Switching Devices and Circuits
Method of Manufacturing an Adaptive Algan Buffer Layer
Monolithically Integrated Vertical Power Transistor and Bypass Diode
Power Module
Patent:
909,310 →
Application:
29/663,502 →
Gan Boule Grown from Liquid Melt Using Gan Seed Wafers
Methods of Treating a Silicon Carbide Substrate for Improved Epitaxial Deposition and Resulting Structures and Devices
Methods for Controlling Formation of Deposits in a Deposition System and Deposition Methods Including the Same
Phase Controlled Sublimation
Methods for Dynamically Controlling a Semiconductor Dicing Saw
Trench Cut Light Emitting Diodes and Methods of Fabricating Same
Nitride-Based Transistors and Methods of Fabrication Thereof Using Non-Etched Contact Recesses
Heterogeneous Bandgap Structures for Semiconductor Devices and Manufacturing Methods Therefor
Growth of Ultra-High Purity Silicon Carbide Crystals in an Ambient Containing Hydrogen
Reducing Nitrogen Content in Silicon Carbide Crystals by Sublimation Growth in a Hydrogen-Containing Ambient
Nitrogen Passivation of Interface States in SIO2/Sic Structures
Method to Reduce Stacking Fault Nucleation Sites and Reduce Forward Voltage Drift in Bipolar Devices
Methods of Forming Power Semiconductor Devices Using Boule-Grown Silicon Carbide Drift Layers and Power Semiconductor Devices Formed Thereby
Vertical Jfet Limited Silicon Carbide Power Metal-Oxide Semiconductor Field Effect Transistors
Large Area, Uniformly Low Dislocation Density Gan Substrate and Process for Making the Same
Vicinal Gallium Nitride Substrate for High Quality Homoepitaxy
Multiple Floating Guard Ring Edge Termination for Silicon Carbide Devices
Semiconductor Substrate Assemblies and Methods for Preparing and Dicing the Same
Co-Doping for Fermi Level Control in Semi-Insulating Group Iii Nitrides
Nitride-Based Transistors with a Protective Layer and a Low-Damage Recess and Methods of Fabrication Thereof
Silicon Carbide on Diamond Substrates and Related Devices and Methods
Nitride Heterojunction Transistors Having Charge-Transfer Induced Energy Barriers and Methods of Fabricating the Same
Reduction of Carrot Defects in Silicon Carbide Epitaxy
Doping of Gallium Nitride by Solid Source Diffusion and Resulting Gallium Nitride Structures
Laser Patterning of Light Emitting Devices
Semiconductor Devices Having a Hybrid Channel Layer, Current Aperture Transistors and Methods of Fabricating Same
Methods of Fabricating Nitride-Based Transistors Having Regrown Ohmic Contact Regions
Dielectric Passivation for Semiconductor Devices
Vapor Assisted Growth of Gallium Nitride
Cascode Amplifier Structures Including Wide Bandgap Field Effect Transistor with Field Plates
Methods of Fabricating Silicon Carbide Devices with Hybrid Well Regions
One Hundred Millimeter High Purity Semi-Insulating Single Crystal Silicon Carbide Wafer
Methods of Fabricating Nitride-Based Transistors with a Cap Layer and a Recessed Gate
Seed and Seedholder Combinations for High Quality Growth of Large Silicon Carbide Single Crystals
Multi-Chamber Mocvd Growth Apparatus for High Performance/High Throughput
Lithographic Methods to Reduce Stacking Fault Nucleation Sites
Silicon Carbide Semiconductor Structures Including Multiple Epitaxial Layers Having Sidewalls
Wide Bandgap Transistor Devices with Field Plates
Lateral Field Effect Transistor and Its Fabrication Comprising a Spacer Layer Above and Below the Channel Layer
Wide Bandgap Hemts with Source Connected Field Plates
Wide Bandgap Field Effect Transistors with Source Connected Field Plates
High Voltage Switching Devices and Process for Forming Same
Wide Bandgap Transistors with Multiple Field Plates
Metal-Semiconductor Field Effect Transistors (Mesfets) Having Drains Coupled to the Substrate and Methods of Fabricating the Same
Asymetric Layout Structures for Transistors and Methods of Fabricating the Same
Reduction of Subsurface Damage in the Production of Bulk Sic Crystals
Transistors Having Buried N-Type and P-Type Regions Beneath the Source Region
Process for Producing High Quality Large Size Silicon Carbide Crystals
Transistors Having Buried N-Type and P-Type Regions Beneath the Source Region and Methods of Fabricating the Same
Methods of Treating a Silicon Carbide Substrate for Improved Epitaxial Deposition and Resulting Structures and Devices
Process for Producing Silicon Carbide Crystals Having Increased Minority Carrier Lifetimes
Method of Forming Semi-Insulating Silicon Carbide Single Crystal
High Electron Mobility Transistor
Vertical Junction Field Effect Transistor Having an Epitaxial Gate
Method of Manufacturing a Vertical Junction Field Effect Transistor Having an Epitaxial Gate
Apparatus and Method for the Production of Bulk Silicon Carbide Single Crystals
Methods of Fabricating Silicon Nitride Regions in Silicon Carbide and Resulting Structures
Three Inch Silicon Carbide Wafer with Low Warp, Bow, and Ttv
Composite Substrates of Conductive and Insulating or Semi-Insulating Group Iii-Nitrides for Group Iii-Nitride Devices
Devices Having Thick Semi-Insulating Epitaxial Gallium Nitride Layer
Aluminum Free Group Iii-Nitride Based High Electron Mobility Transistors
Binary Group Iii-Nitride Based High Electron Mobility Transistors
Silicon carbide junction barrier schottky diodes with supressed minority carrier injection
Method and Apparatus for the Production of Silicon Carbide Crystals
High Voltage Silicon Carbide Mos-Bipolar Devices Having Bi-Directional Blocking Capabilities
High Voltage Silicon Carbide Devices Having Bi-Directional Blocking Capabilities
Methods of Fabricating Silicon Carbide Devices Having Smooth Channels
Fluid-Dispensing Apparatus with Controlled Tear-Off
Low Basal Plane Dislocation Bulk Grown Sic Wafers
Gallium Nitride Based High-Electron Mobility Devices
Method of Manufacturing Gallium Nitride Based High-Electron Mobility Devices
Highly Uniform Group Iii Nitride Epitaxial Layers on 100 Millimeter Diameter Silicon Carbide Substrates
Semiconductor Devices Having Varying Electrode Widths to Provide Non-Uniform Gate Pitches and Related Methods
High Voltage Silicon Carbide Devices Having Bi-Directional Blocking Capabilities
Low dislocation density group III nitride layers on silicon carbide substrates and methods of making the same
Passivation of Wide Band-Gap Based Semiconductor Devices with Hydrogen-Free Sputtered Nitrides
Semiconductor Device Comprising a Junction Having a Plurality of Rings
Methods, Apparatus and Computer Program Products for Controlling a Volume of Liquid in Semiconductor Processing Based on Reflected Optical Radiation
Double Side Polished Wafer Scratch Inspection Tool
Nitride-Based Transistors and Methods of Fabrication Thereof Using Non-Etched Contact Recesses
Method of Manufacturing Carrier Wafer and Resulting Carrier Wafer Structures
Gas driven rotation apparatus and method for forming crystalline layers
Directed Reagents to Improve Material Uniformity
Silicon Carbide Bipolar Junction Transistors Having Epitaxial Base Regions and Multilayer Emitters and Methods of Fabricating the Same
Methods of Fabricating Oxide Layers on Silicon Carbide Layers Utilizing Atomic Oxygen
Methods of Treating a Silicon Carbide Substrate for Improved Epitaxial Deposition and Resulting Structures and Devices
Producing High Quality Bulk Silicon Carbide Single Crystal by Managing Thermal Stresses at a Seed Interface
One Hundred Millimeter Single Crystal Silicon Carbide Wafer
One Hundred Millimeter Single Crystal Silicon Carbide Wafer
Seeded Single Crystal Silicon Carbide Growth and Resulting Crystals
Methods of Fabricating Silicon Carbide Devices Including Multiple Floating Guard Ring Edge Termination
Trench Cut Light Emitting Diodes and Methods of Fabricating Same
Restricted Radiated Heating Assembly for High Temperature Processing
Methods of Manufacturing Group Iii Nitride Semiconductor Devices with Silicon Nitride Layers
High Power, High Frequency Switch Circuits Using Strings of Power Transistors
Semiconductor Devices Including Implanted Regions and Protective Layers and Methods of Forming the Same
Silicon Carbide Bipolar Junction Transistors Having a Silicon Carbide Passivation Layer on the Base Region Thereof
Methods of Fabricating Strain Balanced Nitride Heterojunction Transistors
Environmentally Robust Passivation Structures for High-Voltage Silicon Carbide Semiconductor Devices
Edge termination structures for silicon carbide devices
Methods of Fabricating Transistors Including Supported Gate Electrodes
Dispensed Electrical Interconnections
Silicon Carbide Layer on Diamond Substrate for Supporting Group Iii Nitride Heterostructure Device
Heterojunction Transistors Including Energy Barriers
Nitride-Based Transistors with a Protective Layer and a Low-Damage Recess
High power silicon carbide (SiC) PiN diodes having low forward voltage drops
Method and Device of Field Effect Transistor Including a Base Shorted to a Source Region
Method to Reduce Stacking Fault Nucleation Sites and Reduce Vf Drift in Bipolar Devices
Vicinal Gallium Nitride Substrate for High Quality Homoepitaxy
Method of Fabricating Seminconductor Devices Including Self Aligned Refractory Contacts
Methods for Fabricating Semiconductor Devices Having Reduced Implant Contamination
Methods for Reducing Contamination of Semiconductor Devices and Materials During Wafer Processing
High-Temperature Ion Implantation Apparatus and Methods of Fabricating Semiconductor Devices Using High-Temperature Ion Implantation
Semiconductor Device
Sequential Lithographic Methods to Reduce Stacking Fault Nucleation Sites
One Hundred Millimeter SiC Crystal Grown on Off-Axis Seed
Robust Transistors with Fluorine Treatment
Methods of Forming Sic Mosfets with High Inversion Layer Mobility
Methods of Fabricating Transistors Including Dielectrically-Supported Gate Electrodes
Semiconductor Devices Including Schottky Diodes with Controlled Breakdown
Reduced Leakage Power Devices by Inversion Layer Surface Passivation
Structure and Method for Reducing Forward Voltage Across a Silicon Carbide-Group Iii Nitride Interface
Heat Sink Assembly and Related Methods for Semiconductor Vacuum Processing Systems
Deposition Systems and Susceptor Assemblies for Depositing a Film on a Substrate
Silicon Carbide Devices with Hybrid Well Regions
Methods of Processing Semiconductor Wafers Having Silicon Carbide Power Devices Thereon
Co-Doping for Fermi Level Control in Semi-Insulating Group Iii Nitrides
Transistors Having Buried P-Type Layers Coupled to the Gate
Integrated Circuit Esd Protection
Methods and Apparatus for Reducing Buildup of Deposits in Semiconductor Processing Equipment
Power Switching Semiconductor Devices Including Rectifying Junction-Shunts
Sublimation Chamber for Phase Controlled Sublimation
Semiconductor Devices Including Implanted Regions for Providing Low-Resistance Contact to Buried Layers and Related Devices
High Voltage Gan Transistors
Epitaxial Semiconductor Structures Having Reduced Stacking Fault Nucleation Sites
Feature Forming Methods to Reduce Stacking Fault Nucleation Sites
Silicon Carbide Dimpled Substrate
Low Voltage Diode with Reduced Parasitic Resistance and Method for Fabricating
Transistors Having Implanted Channels and Implanted P-Type Regions Beneath the Source Region
Seed and Seedholder Combinations for High Quality Growth of Large Silicon Carbide Single Crystals
Schottky Diode Structure with Silicon Mesa and Junction Barrier Schottky Wells
Methods of Fabricating Vertical Jfet Limited Silicon Carbide Metal-Oxide Semiconductor Field Effect Transistors
Insulated Gate Bipolar Transistors Including Current Suppressing Layers
Silicon Carbide Self-Aligned Epitaxial Mosfet for High Powered Device Applications
Nitride Semiconductor Structures with Interlayer Structures
Thick Nitride Semiconductor Structures with Interlayer Structures
Cap Layers Including Aluminum Nitride for Nitride-Based Transistors
High Temperature Performance Capable Gallium Nitride Transistor
Polytype Hetero-Interface High Electron Mobility Device and Method of Making
Methods of Forming Silicon Carbide Switching Devices Including P-Type Channels
Reduction of Carrot Defects in Silicon Carbide Epitaxy
Wide Bandgap Transistor Devices with Field Plates
Silicon Carbide Power Devices Including P-Type Epitaxial Layers and Direct Ohmic Contacts
Methods of Fabricating Nitride-Based Transistors with a Cap Layer and a Recessed Gate
Methods of Forming Ohmic Layers Through Ablation Capping Layers
High Power Insulated Gate Bipolar Transistors
Selective Wet Etching of Gold-Tin Based Solder
Passivation of Wide Band-Gap Based Semiconductor Devices with Hydrogen-Free Sputtered Nitrides
Halogen Assisted Physical Vapor Transport Method for Silicon Carbide Growth
High Temperature Ion Implantation of Nitride Based Hemts
Micropipe-Free Silicon Carbide and Related Method of Manufacture
Micropipe-Free Silicon Carbide and Related Method of Manufacture
Gan Based Hemts with Buried Field Plates
Grid-Umosfet with Electric Field Shielding of Gate Oxide
Large Area, Uniformly Low Dislocation Density Gan Substrate and Process for Making the Same
Insulated Gate Bipolar Conduction Transistors (Ibcts) and Related Methods of Fabrication
Current Aperture Transistors and Methods of Fabricating Same
Transistors and Method for Making Ohmic Contact to Transistors
Wireless Telemetry for Instrumented Component
Low Micropipe 100 mm Silicon Carbide Wafer
Low 1C Screw Dislocation 3 Inch Silicon Carbide Wafer
Short Gate High Power Mosfet and Method of Manufacture
Transistor with a-Face Conductive Channel and Trench Protecting Well Region
Pendeo Epitaxial Structures and Devices
Metallization structure for high power microelectronic devices
Semiconductor Transistor with P Type Re-Grown Channel Layer
Silicon-Rich Nickel-Silicide Ohmic Contacts for Sic Semiconductor Devices
Large Area, Uniformly Low Dislocation Density Gan Substrate and Process for Making the Same
Double Guard Ring Edge Termination for Silicon Carbide Devices
Integrated Nitride and Silicon Carbide-Based Devices and Methods of Fabricating Integrated Nitride-Based Devices
Vicinal Gallium Nitride Substrate for High Quality Homoepitaxy
Methods of Forming Group Iii-Nitride Semiconductor Devices Including Implanting Ions Directly into Source and Drain Regions and Annealing to Activate the Implanted Ions
Highly Uniform Group Iii Nitride Epitaxial Layers on 100 Millimeter Diameter Silicon Carbide Substrates
Methods for Controllably Induction Heating an Article
Junction Barrier Schottky Diodes with Current Surge Capability
Normally-Off Semiconductor Devices
Semiconductor Devices Including Implanted Regions and Protective Layers
Mesa Termination Structures for Power Semiconductor Devices Including Mesa Step Buffers
Wireless Telemetry Circuit Structure for Measuring Temperature in High Temperature Environments
Methods of Fabricating Silicon Carbide Devices Incorporating Multiple Floating Guard Ring Edge Terminations
Power Semiconductor Devices with Mesa Structures and Buffer Layers Including Mesa Steps
Printed Circuit Board for Harsh Environments
Methods of Passivating Surfaces of Wide Bandgap Semiconductor Devices
A Semiconductor Device
Wide Bandgap Transistor Devices with Field Plates
Passivation of Wide Band-Gap Based Semiconductor Devices with Hydrogen-Free Sputtered Nitrides
Bidirectional Silicon Carbide Transient Voltage Suppression Devices
Rectifier with Sic Bipolar Junction Transistor Rectifying Elements
Methods of Forming Semiconductor Devices Including Epitaxial Layers and Related Structures
High-Temperature Ion Implantation Apparatus and Methods of Fabricating Semiconductor Devices Using High-Temperature Ion Implantation
Silicon Carbide Devices Having Smooth Channels
Wide Bandgap Hemts with Source Connected Field Plates
Wide Bandgap Bipolar Turn-Off Thyristor Having Non-Negative Temperature Coefficient and Related Control Circuits
Schottky Diodes Containing High Barrier Metal Islands in a Low Barrier Metal Layer and Methods of Forming the Same
Transistors Including Supported Gate Electrodes
Methods of Processing Semiconductor Wafers Having Silicon Carbide Power Devices Thereon
Schottky Diodes Including Polysilicon Having Low Barrier Heights and Methods of Fabricating the Same
Semiconductor Devices Including Schottky Diodes Having Doped Regions Arranged as Islands and Methods of Fabricating Same
Wide Bandgap Transistors with Multiple Field Plates
Methods of Fabricating Oxide Layers on Silicon Carbide Layers Utilizing Atomic Oxygen
High-Gain Wide Bandgap Darlington Transistors and Related Methods of Fabrication
High Breakdown Voltage Wide Band-Gap Mos-Gated Bipolar Junction Transistors with Avalanche Capability
Silicon Carbide on Diamond Substrates and Related Devices and Methods
High Speed Rectifier Circuit
Semiconductor Devices Including Electrodes with Integrated Resistances
Semiconductor Devices with Current Shifting Regions and Related Methods
Transistors with a Gate Insulation Layer Having a Channel Depleting Interfacial Charge and Related Fabrication Methods
Solid-State Pinch Off Thyristor Circuits
Electronic Device Submounts with Thermally Conductive Vias and Light Emitting Devices Including the Same
High Voltage Insulated Gate Bipolar Transistors with Minority Carrier Diverter
Methods of Forming Power Switching Semiconductor Devices Including Rectifying Junction-Shunts
Nitride-Based Transistors Having Laterally Grown Active Region and Methods of Fabricating Same
Low-Loss Noise-Resistant High-Temperature Gate Driver Circuits
Patent:
7,965,522 →
Application:
12/586,729 →
Heterojunction Transistors Having Barrier Layer Bandgaps Greater Than Channel Layer Bandgaps and Related Methods
Transistors with Semiconductor Interconnection Layers and Semiconductor Channel Layers of Different Semiconductor Materials
Methods of Fabricating Transistors Using Laser Annealing of Source/Drain Regions
Robust Transistors with Fluorine Treatment
Method of Manufacturing Silicon Carbide Self-Aligned Epitaxial Mosfet for High Powered Device Applications
Monolithic High Voltage Switching Devices
Power Switching Devices Having Controllable Surge Current Capabilities
Power Semiconductor Devices Having Selectively Doped Jfet Regions and Related Methods of Forming Such Devices
Devices with Crack Stops
Methods of Fabricating Transistors Having Buried P-Type Layers Coupled to the Gate
High Voltage Gan Transistors
Semiconductor Device Structures with Modulated Doping and Related Methods
Restricted Radiated Heating Assembly for High Temperature Processing
Nitride-Based Transistors with a Cap Layer and a Recessed Gate
Growing Polygonal Carbon from Photoresist
Methods of Forming Contact Structures Including Alternating Metal and Silicon Layers and Related Devices
Vicinal Gallium Nitride Substrate for High Quality Homoepitaxy
Diffused Junction Termination Structures for Silicon Carbide Devices and Methods of Fabricating Silicon Carbide Devices Incorporating Same
Semiconductor Devices with Heterojunction Barrier Regions and Methods of Fabricating Same
Methods of Fabricating Transistors Including Dielectrically-Supported Gate Electrodes and Related Devices
Multilayer Diffusion Barriers for Wide Bandgap Schottky Barrier Devices
Wide Band-Gap MOSFETs Having a Heterojunction Under Gate Trenches Thereof and Related Methods of Forming Such Devices
Semiconductor Devices Having Improved Adhesion and Methods of Fabricating the Same
Method for Controlled Growth of Silicon Carbide and Structures Produced by Same
One Hundred Millimeter Single Crystal Silicon Carbide Wafer
Multi-Chamber Mocvd Growth Apparatus for High Performance/High Throughput
Patent:
43,045 →
Application:
12/774,345 →
Methods of Forming Sic Mosfets with High Inversion Layer Mobility
Semiconductor Devices Having Gates Including Oxidized Nickel
Smoothing Method for Semiconductor Material and Wafers Produced by Same
Diode Having Reduced on-Resistance and Associated Method of Manufacture
Power Converter Circuits Including High Electron Mobility Transistors for Switching and Rectifcation
Electronic Device Structure Including a Buffer Layer on a Base Layer
Electronic Device Structure with a Semiconductor Ledge Layer for Surface Passivation
Semiconductor Device Structures with Modulated and Delta Doping and Related Methods
Patent:
8,536,615 →
Application:
12/848,600 →
Circuit Breaker
Process for Producing Silicon Carbide Crystals Having Increased Minority Carrier Lifetimes
Semiconductor Device with Protecting Film and Method of Fabricating the Semiconductor Device with Protecting Film
Methods of Forming Semiconductor Contacts
Normally-Off D-Mode Driven Direct Drive Cascode
Patent:
8,228,114 →
Application:
12/924,622 →
Multi-Rotation Epitaxial Growth Apparatus and Reactors Incorporating Same
Low Voltage Diode with Reduced Parasitic Resistance and Method for Fabricating
Methods of Fabricating Nitride Semiconductor Structures with Interlayer Structures
Contact Pad
Wafer Precursor Prepared for Group Iii Nitride Epitaxial Growth on a Composite Substrate Having Diamond and Silicon Carbide Layers, and Semiconductor Laser Formed Thereon
Apparatus for Reducing Buildup of Deposits in Semiconductor Processing Equipment
Low Dislocation Density Iii-V Nitride Substrate Including Filled Pits and Process for Making the Same
Group Iii Nitride Semiconductor Devices with Silicon Nitride Layers and Methods of Manufacturing Such Devices
High Voltage Gan Transistors
Instrumented Component for Wireless Telemetry
Silicon Carbide Switching Devices Including P-Type Channels
Nitride-Based Transistors With a Protective Layer and a Low-Damage Recess
Junction Termination Structures Including Guard Ring Extensions and Methods of Fabricating Electronic Devices Incorporating Same
Integrated Nitride and Silicon Carbide-Based Devices
Semiconductor Device Having High Performance Channel
Vertical Jfet Limited Silicon Carbide Metal-Oxide Semiconductor Field Effect Transistors
Semiconductor Devices Including Schottky Diodes Having Overlapping Doped Regions and Methods of Fabricating Same
Wide Bandgap Hemts with Source Connected Field Plates
Recessed Termination Structures and Methods of Fabricating Electronic Devices Including Recessed Termination Structures
Coupled Inductor Output Filter
Patent:
8,427,120 →
Application:
13/068,229 →
Field Effect Transistor Devices with Low Source Resistance
Field Effect Transistor Devices with Low Source Resistance
Sic Devices with High Blocking Voltage Terminated by a Negative Bevel
Robust Transistors with Fluorine Treatment
Thin Film Resistor
Transistor with a-Face Conductive Channel and Trench Protecting Well Region
Methods of Fabricating Normally-Off Semiconductor Devices
Method of Producing High Quality Silicon Carbide Crystal in a Seeded Growth System
Ohmic Contact to Semiconductor Device
Ohmic Contact Structure for Group Iii Nitride Semiconductor Device Having Improved Surface Morphology and Well-Defined Edge Features
System and Method for Wafer Level Packaging
Forming Sic Mosfets with High Channel Mobility by Treating the Oxide Interface with Cesium Ions
Wet Chemistry Processes for Fabricating a Semiconductor Device with Increased Channel Mobility
Semiconductor Device with Increased Channel Mobility and Dry Chemistry Processes for Fabrication Thereof
Schottky Diode
Edge Termination Structure Employing Recesses for Edge Termination Elements
Schottky Diode Employing Recesses for Elements of Junction Barrier Array
Gan Based Hemts with Buried Field Plates
Power Switching Semiconductor Devices Including Rectifying Junction-Shunts
Bipolar Junction Transistor Structure for Reduced Current Crowding
Mesa Termination Structures for Power Semiconductor Devices and Methods of Forming Power Semiconductor Devices with Mesa Termination Structures
Wide Bandgap Transistor Devices with Field Plates
Sic Devices with High Blocking Voltage Terminated by a Negative Bevel
Semiconductor Device and Fabrication Method for the Same
High Voltage Semiconductor Devices Including Electric Arc Suppression Material and Methods of Forming the Same
Schottky Contact
Localized Annealing of Metal-Silicon Carbide Ohmic Contacts and Devices So Formed
Polymer via Plugs with High Thermal Integrity
Pcb Based Rf-Power Package Window Frame
Stable Power Devices on Low-Angle Off-Cut Silicon Carbide Crystals
High Voltage Driver
Bipolar Junction Transistor with Improved Avalanche Capability
High Voltage Gan Transistor
Optically Assist-Triggered Wide Bandgap Thyristors Having Positive Temperature Coefficients
Methods of Fabricating Silicon Carbide Devices Having Smooth Channels
High Temperature Performance Capable Gallium Nitride Transistor
Transistor with a-Face Conductive Channel and Trench Protecting Well Region
Normally-Off Semiconductor Devices
High Temperature Half Bridge Gate Driver
Voltage Regulator Circuitry Operable in a High Temperature Environment of a Turbine Engine
Junction Barrier Schottky Diodes with Current Surge Capability
Monolithic Bidirectional Silicon Carbide Switching Devices
Power Module for Supporting High Current Densities
Semiconductor Devices with Non-Implanted Barrier Regions and Methods of Fabricating Same
Semiconductor Devices Including Epitaxial Layers and Related Methods
Using a Carbon Vacancy Reduction Material to Increase Average Carrier Lifetime in a Silicon Carbide Semiconductor Device
Predisposed High Electron Mobility Transistor
Hydrogen Mitigation Schemes in the Passivation of Advanced Devices
Using Stress Reduction Barrier Sub-Layers in a Semiconductor Die
Increased Transition Speed Switching Device Driver
Ni-Rich Schottky Contact
Super Surge Diodes
Schottky Structure Employing Central Implants Between Junction Barrier Elements
Low Voltage Diode with Reduced Parasitic Resistance and Method for Fabricating
Devices with Crack Stops
Dielectric Solder Barrier for Semiconductor Devices
Transistor Structures Having Reduced Electrical Field at the Gate Oxide and Methods for Making Same
Transistor Structures Having a Deep Recessed P+ Junction and Methods for Making Same
Thick Nitride Semiconductor Structures with Interlayer Structures and Methods of Fabricating Thick Nitride Semiconductor Structures
Method for Controlled Growth of Silicon Carbide and Structures Produced by Same
Mix Doping of a Semi-Insulating Group Iii Nitride
Low 1C Screw Dislocation 3 Inch Silicon Carbide Wafer
Tunnel Junction Field Effect Transistors Having Self-Aligned Source and Gate Electrodes and Methods of Forming the Same
Floating Bond Pad for Power Semiconductor Devices
Field Effect Transistor Devices with Protective Regions
Field Effect Transistor Devices with Regrown P-Layers
Field Effect Transistor Devices with Buried Well Protection Regions
Field Effect Transistor Devices with Buried Well Regions and Epitaxial Layers
Gate Contact for a Semiconductor Device and Methods of Fabrication Thereof
Encapsulation of Advanced Devices Using Novel Pecvd and Ald Schemes
Low Loss Electronic Devices Having Increased Doping for Reduced Resistance and Methods of Forming the Same
Wafer-Level Die Attach Metallization
Grid-Umosfet with Electric Field Shielding of Gate Oxide
Bidirectional Silicon Carbide Transient Voltage Supression Devices
Smoothing Method for Semiconductor Material and Wafers Produced by Same
Autonomous Temperature Accelerometer Sensor
Patent:
9,435,819 →
Application:
13/872,505 →
Silver Filled Trench Substrate for High Power and/or High Temperature Electronics
Patent:
9,615,452 →
Application:
13/891,720 →
High Temperature Magnetic Amplifiers
Patent:
9,118,289 →
Application:
13/891,787 →
Methods of Fabricating Nitride-Based Transistors with an Etch Stop Layer
High Performance Power Module
Hybrid Semiconductor Package
Cascode Structures for Gan Hemts
Vertical Power Transistor with Built-in Gate Buffer
Recessed Field Plate Transistor Structures
Enhanced Gate Dielectric for a Field Effect Device with a Trenched Gate
Methods of Forming Junction Termination Extension Edge Terminations for High Power Semiconductor Devices and Related Semiconductor Devices
Wide Bandgap Device Having a Buffer Layer Disposed Over a Diamond Substrate
Vertical Power Transistor Device
Edge Termination Technique for High Voltage Power Devices Having a Negative Feature for an Improved Edge Termination Structure
Methods of Fabricating Thick Semi-Insulating or Insulating Epitaxial Gallium Nitride Layers
Low Profile High Temperature Double Sided Flip Chip Power Packaging
Patent:
9,275,938 →
Application:
14/016,728 →
CASCODE STRUCTURES WITH GaN CAP LAYERS
Semiconductor Device Including a Power Transistor Device and Bypass Diode
Layout Configurations for Integrating Schottky Contacts into a Power Transistor Device
Boost Converter with Reduced Switching Loss and Methods of Operating the Same
Devices Including Ultra-Short Gates and Methods of Forming Same
Thin Film Resistor
Field Effect Device with Enhanced Gate Dielectric Structure
Semiconductor Devices in Sic Using Vias Through N-Type Substrate for Backside Contact to P-Type Layer
High Temperature Equalized Electrical Parasitic Power Packaging Method for Many Paralleled Semiconductor Power Devices
Patent:
9,095,054 →
Application:
14/054,089 →
Low Micropipe 100 Mm Silicon Carbide Wafer
Method for Reworkable Packaging of High Speed, Low Electrical Parasitic Power Electronics Modules Through Gate Drive Integration
Patent:
9,407,251 →
Application:
14/100,288 →
Diffused Junction Termination Structures for Silicon Carbide Devices
Schottky Diode
Stress Mitigation for Thin and Thick Films Used in Semiconductor Circuitry
Apparatus Having Self Healing Liquid Phase Power Connects and Method Thereof
Patent:
9,728,868 →
Application:
14/176,494 →
Method of Manufacturing Precise Semiconductor Contacts
Power Conversion Electronics Having Conversion and Inverter Circuitry
Semiconductor Device with Self-Aligned Ohmic Contacts
Converter Circuitry
Seminconductor Device with Spreading Layer
High Power Insulated Gate Bipolar Transistors
HIGH CURRENT, LOW SWITCHING LOSS SiC POWER MODULE
Controlled Ion Implantation Into Silicon Carbide Using Channeling And Devices Fabricated Using Controlled Ion Implantation Into Silicon Carbide Using Channeling
Over-Mold Packaging for Wide Band-Gap Semiconductor Devices
Methods of Forming Buried Junction Devices in Silicon Carbide Using Ion Implant Channeling and Silicon Carbide Devices Including Buried Junctions
Igbt with Bidirectional Conduction
Step Etched Metal Electrical Contacts
Patent:
9,967,977 →
Application:
14/308,283 →
Multi-Module, Scalable, High Power Density, Radiation-Hardened Power Converter Interface System
Patent:
9,419,448 →
Application:
14/308,308 →
Non Linear Resonant Switch Cell
Patent:
9,559,684 →
Application:
14/309,155 →
Electronic Device Structure with a Semiconductor Ledge Layer for Surface Passivation
Junction Termination Structures Including Guard Ring Extensions and Methods of Fabricating Electronic Devices Incorporating Same
Methods of Fabricating Semiconductor Devices Including Implanted Regions for Providing Low-Resistance Contact to Buried Layers and Related Devices
Transistors with a Gate Insulation Layer Having a Channel Depleting Interfacial Charge
Insulated Gate Bipolar Transistors Including Current Suppressing Layers
Silicon Carbide Devices Having Smooth Channels
High Power Density, High Efficiency Power Electronic Converter
Passivation Structure for Semiconductor Devices
Power Converter Circuits Including High Electron Mobility Transistors for Switching and Rectification
Semiconductor Devices with Heterojunction Barrier Regions and Methods of Fabricating Same
High Voltage Power Chip Module
Semiconductor Device with Improved Field Plate
Semiconductor Device with Improved Field Plate
A Semiconductor Package Having a Baseplate with a Die Attach Region and a Peripheral Region
Semiconductor Device with Improved Insulated Gate
Monolithic Bidirectional Silicon Carbide Switching Devices
Pecvd Protective Layers for Semiconductor Devices
Power Semiconductor Devices Having Superjunction Structures with Implanted Sidewalls
Wafer-Level Die Attach Metallization
Gate Contact for a Semiconductor Device and Methods of Fabrication Thereof
Low Profile, Highly Configurable, Current Sharing Paralleled Wide Band Gap Power Device Power Module
Active Energy Recovery Clamping Circuit to Improve the Performance of Power Converters
Patent:
9,647,563 →
Application:
14/634,252 →
Multi-Cavity Package Having Single Metal Flange
Hybrid Analog and Digital Power Converter Controller
High Voltage Gan Transistor
Surface Mount Device with Stress Mitigation Measures
Patent:
9,450,163 →
Application:
14/721,525 →
Schottky Diode
PCB Based Semiconductor Package Having Integrated Electrical Functionality
Field Effect Transistor Devices with Buried Well Protection Regions
High Voltage Power Module
Optically Assist-Triggered Wide Bandgap Thyristors Having Positive Temperature Coefficients
Tunnel Junction Field Effect Transistors Having Self-Aligned Source and Gate Electrodes and Methods of Forming the Same
Method and Device for a High Temperature Vacuum-Safe Solder Stop Utilizing Laser Processing of Solderable Surfaces for an Electronic Module Assembly
High Speed, Efficient Sic Power Module
High Current, Low Switching Loss Sic Power Module
Schottky Structure Employing Central Implants Between Junction Barrier Elements
Vertical Power Transistor Device
Super Junction Power Semiconductor Devices Formed via Ion Implantation Channeling Techniques and Related Methods
Gallium Nitride High-Electron Mobility Transistors with P-Type Layers and Process for Making the Same
Low Profile, Highly Configurable, Current Sharing Paralleled Wide Band Gap Power Device Power Module
High Speed, Efficient Sic Power Module
Methods of Forming Buried Junction Devices in Silicon Carbide Using Ion Implant Channeling and Silicon Carbide Devices Including Buried Junctions
Methods of Forming Power Semiconductor Devices Having Superjunction Structures with Pillars Having Implanted Sidewalls
Transistor Structures Having Reduced Electrical Field at the Gate Oxide and Methods for Making Same
Power Schottky Diodes Having Local Current Spreading Layers and Methods of Forming Such Devices
Patent:
9,929,284 →
Application:
15/349,092 →
Ohmic Contact Structure for Group Iii Nitride Semiconductor Device Having Improved Surface Morphology and Well-Defined Edge Features
Power Semiconductor Devices Having Gate Trenches with Implanted Sidewalls and Related Methods
Patent:
9,887,287 →
Application:
15/372,516 →
Power Semiconductor Devices Having Gate Trenches and Buried Edge Terminations and Related Methods
Field Effect Transistor Devices with Buried Well Protection Regions
Power Modules Having an Integrated Clamp Circuit and Process Thereof
Stabilized, High-Doped Silicon Carbide
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Vertical Fet Structure
Gallium Nitride High-Electron Mobility Transistors with Deep Implanted P-Type Layers in Silicon Carbide Substrates for Power Switching and Radio Frequency Applications and Process for Making the Same
Power Modules Having an Integrated Clamp Circuit and Process Thereof
Power Module Having a Switch Module for Supporting High Current Densities
Low Switching Loss High Performance Power Module
Power Module with Improved Reliability
Patent:
9,998,109 →
Application:
15/594,868 →
Semiconductor Devices Having a Plurality of Unit Cell Transistors That Have Smoothed Turn-on Behavior and Improved Linearity
Depletion Mode Semiconductor Devices Including Current Dependent Resistance
Power Schottky Diodes Having Closely-Spaced Deep Blocking Junctions in a Heavily-Doped Drift Region
Die-Attach Method to Compensate for Thermal Expansion
Wide Bandgap Field Effect Transistors with Source Connected Field Plates
Power Switching Devices with Dv/Dt Capability and Methods of Making Such Devices
Controlled Ion Implantation into Silicon Carbide Using Channeling and Devices Fabricated Using Controlled Ion Implantation into Silicon Carbide Using Channeling
RF Amplifier Package with Biasing Strip
Patent:
10,141,303 →
Application:
15/709,532 →
Totem Pole Pfc Converter and System
Patent:
10,224,809 →
Application:
15/725,324 →
Rivetless Lead Fastening for a Semiconductor Package
High Voltage Power Module
Semiconductor Die with Improved Ruggedness
Power Silicon Carbide Based Mosfet Transistors with Improved Short Circuit Capabilities and Methods of Making Such Devices
Vertical Semiconductor Device with Improved Ruggedness
Silicon Carbide Power Module
Vertical Power Transistor Device
Patent:
48,380 →
Application:
15/970,148 →
Power Module with Improved Reliability
High Power Transistor with Interior-Fed Gate Fingers
Patent:
10,483,352 →
Application:
16/032,571 →
Wide Bandgap Semiconductor Device
Power Module
Patent:
954,667 →
Application:
29/663,171 →
Power Module
Patent:
903,590 →
Application:
29/663,172 →
Power Module
Patent:
908,632 →
Application:
29/663,505 →
Method and Device for a High Temperature Vacuum-Safe Solder Resist Utilizing Laser Ablation of Solderable Surfaces for an Electronic Module Assembly
RF Amplifier Package with Biasing Strip
Transistor Structures Having a Deep Recessed P+ Junction and Methods for Making Same
Power Module for Supporting High Current Densities
Field Effect Transistor Devices with Buried Well Protection Regions
High Electron Mobility Transistors Having Improved Drain Current Drift and/or Leakage Current Performance
Housing for a Power Module Assembly
Patent:
954,668 →
Application:
29/676,416 →
Gallium Nitride High-Electron Mobility Transistors with Deep Implanted P-Type Layers in Silicon Carbide Substrates for Power Switching and Radio Frequency Applications and Process for Making the Same
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Methods and Apparatuses Related to Shaping Wafers Fabricated by Ion Implantation
Carrier-Assisted Method for Parting Crystalline Material Along Laser Damage Region
Laser-Assisted Method for Parting Crystalline Material
Patent:
10,576,585 →
Application:
16/274,064 →
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Power Semiconductor Devices Having Top-Side Metallization Structures That Include Buried Grain Stop Layers
Structures for Reducing Electron Concentration and Process for Reducing Electron Concentration
High Voltage Power Module
Group Iii-Nitride High-Electron Mobility Transistors with Buried P-Type Layers and Process for Making the Same
Transistor Semiconductor Die with Increased Active Area
High Power Transistor with Interior-Fed Fingers
Semiconductor Die with Improved Ruggedness
Laser-Assisted Method for Parting Crystalline Material
Patent:
10,562,130 →
Application:
16/410,487 →
Power Semiconductor Devices Having Reflowed Inter-Metal Dielectric Layers
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
Patent:
10,611,052 →
Application:
16/415,721 →
High Reliability Semiconductor Devices and Methods of Fabricating the Same
Methods for Dicing Semiconductor Wafers and Semiconductor Devices Made by the Methods
High Electron Mobility Transistors Having Improved Contact Spacing and/or Improved Contact Vias
Package for Power Electronics
Device Design for Short-Circuitry Protection Circuitry Within Transistors
Composite-Channel High Electron Mobility Transistor
Depletion Mode Semiconductor Devices Including Current Dependent Resistance
Hybrid Power Module
Overcurrent Protection for Power Transistors
Power Silicon Carbide Based Mosfet Transistors with Improved Short Circuit Capabilities and Methods of Making Such Devices
Contact and Die Attach Metallization for Silicon Carbide Based Devices and Related Methods of Sputtering Eutectic Alloys
Multi-Cavity Package Having Single Metal Flange
High Power Transistor with Interior-Fed Gate Fingers
Systems and Processes for Increasing Semiconductor Device Reliability
Semiconductor Device with Improved Short Circuit Withstand Time and Methods for Manufacturing the Same
Stepped Field Plates with Proximity to Conduction Channel and Related Fabrication Methods
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Power Module Having Pin Fins
Patent:
942,403 →
Application:
29/710,592 →
Passivation Structure for Semiconductor Devices
Patent:
49,167 →
Application:
16/681,044 →
Semiconductors with Improved Thermal Budget and Process of Making Semiconductors with Improved Thermal Budget
Stabilized, High-Doped Silicon Carbide
Dislocation Distribution for Silicon Carbide Crystalline Materials
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
Laser-Assisted Method for Parting Crystalline Material
Patent:
11,219,966 →
Application:
16/792,261 →
Vertical Semiconductor Device with Improved Ruggedness
Alignment for Wafer Images
System and Process for Implementing Accelerated Test Conditions for High Voltage Lifetime Evaluation of Semiconductor Power Devices
Power Switching Devices with High Dv/Dt Capability and Methods of Making Such Devices
Power Semiconductor Package
Patent:
937,231 →
Application:
29/730,568 →
Semiconductor Power Devices Having Gate Dielectric Layers with Improved Breakdown Characteristics and Methods of Forming Such Devices
Interface Layer Control Methods for Semiconductor Power Devices and Semiconductor Devices Formed Thereof
Trenched Power Device with Segmented Trench and Shielding
Integrated Circuit Having Die Attach Materials with Channels and Process of Implementing the Same
Contact Structures for Semiconductor Devices
Semiconductor Power Devices Having Graded Lateral Doping in the Source Region
Power Semiconductor Devices Having Multilayer Gate Dielectric Layers That Include an Etch Stop/Field Control Layer and Methods of Forming Such Devices
High Voltage Power Module
Vertical Semiconductor Device with Improved Ruggedness
Trench Bottom Shielding Methods and Approaches for Trenched Semiconductor Device Structures
Edge Termination Structures for Semiconductor Devices
Power Module Having an Elevated Power Plane with an Integrated Signal Board and Process of Implementing the Same
Power Semiconductor Devices Including a Trenched Gate and Methods of Forming Such Devices
Field Effect Transistor with at Least Partially Recessed Field Plate
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
Semiconductor Die with Improved Ruggedness
Power Module
Patent:
969,740 →
Application:
29/757,360 →
Semiconductor Power Devices Having Multiple Gate Trenches and Methods of Forming Such Devices
Semiconductor Devices for Improved Measurements and Related Methods
High Electron Mobility Transistors Having Improved Drain Current Drift and/or Leakage Current Performance
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Integrated Power Module
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
Semiconductor Devices Having Gate Resistors with Low Variation in Resistance Values
Power Semiconductor Package
Patent:
969,762 →
Application:
29/811,014 →
Power Module Having Pin Fins
Patent:
985,517 →
Application:
29/821,330 →
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 20, 2014
From: PALA, VIPINDAS; VAN BRUNT, EDWARD ROBERT; CHENG, LIN
To: CREE, INC.
Reel/Frame 032484/0824 →
Assignment of Assignor's Interest
Dec 5, 2019
From: LEE, KYOUNG-KEUN
To: CREE, INC.
Reel/Frame 051192/0956 →
Assignment of Assignor's Interest
Dec 6, 2019
From: MARTIN, DANIEL JOHN; CURBOW, WILLIAM AUSTIN
To: CREE FAYETTEVILLE, INC.
Reel/Frame 051205/0172 →
Assignment of Assignor's Interest
May 11, 2020
From: STEINMANN, PHILIPP; VAN BRUNT, EDWARD ROBERT; RYU, SEI-HYUNG; PARK, JAE-HYUNG
To: CREE, INC.
Reel/Frame 052626/0452 →
Assignment of Assignor's Interest
May 18, 2020
From: HARDIMAN, CHRIS; RADULESCU, FABIAN; SHEPPARD, SCOTT; NAMISHIA, DAN
To: CREE, INC.
Reel/Frame 052689/0481 →
Assignment of Assignor's Interest
Jun 2, 2020
From: MCPHERSON, BRICE; MARTIN, DANIEL; LOSTETTER, ALEXANDER
To: CREE FAYETTEVILLE, INC.
Reel/Frame 052813/0193 →
Assignment of Assignor's Interest
Jun 3, 2020
From: MOXEY, GUY; SAXENA, KULDEEP
To: CREE, INC.
Reel/Frame 052821/0101 →
Assignment of Assignor's Interest
Jun 19, 2020
From: LICHTENWALNER, DANIEL JENNER; ISLAM, NAEEM
To: CREE, INC.
Reel/Frame 052994/0867 →
Assignment of Assignor's Interest
Jun 29, 2020
From: LEONARD, ROBERT TYLER; CONRAD, MATTHEW DAVID; VAN BRUNT, EDWARD ROBERT
To: CREE, INC.
Reel/Frame 053071/0434 →
Assignment of Assignor's Interest
Jul 24, 2020
From: MCPHERSON, BRICE
To: CREE FAYETTEVILLE, INC.
Reel/Frame 053304/0690 →
Assignment of Assignor's Interest
Aug 14, 2020
From: LICHTENWALNER, DANIEL J.; ISLMAN, NAEEM; KIM, WOONGSUN; RYU, SEI-HYUNG
To: CREE, INC.
Reel/Frame 053498/0370 →
Assignment of Assignor's Interest
Aug 27, 2020
From: HAN, KIJEONG; KIM, JOOHYUNG; RYU, SEI-HYUNG
To: CREE, INC.
Reel/Frame 053616/0417 →
Assignment of Assignor's Interest
Sep 22, 2020
From: KOVALEVSKII, DMITRI; ADAMSON, TYLER
To: CREE FAYETTEVILLE, INC.
Reel/Frame 053844/0749 →
Assignment of Assignor's Interest
Oct 13, 2020
From: LICHTENWALNER, DANIEL JENNER; KIM, WOONGSUN
To: CREE, INC.
Reel/Frame 054041/0032 →
Assignment of Assignor's Interest
Feb 9, 2021
From: LICHTENWALNER, DANIEL JENNER; VAN BRUNT, EDWARD ROBERT
To: CREE, INC.
Reel/Frame 055199/0059 →
Merger
Aug 13, 2021
From: CREE FAYETTEVILLE, INC.
To: CREE, INC.
Reel/Frame 057291/0406 →
Merger
Oct 8, 2021
From: CREE FAYETTEVILLE, INC.
To: CREE, INC.
Reel/Frame 057738/0781 →
Change of Name
Oct 22, 2021
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 057891/0880 →
Change of Name
Jan 24, 2022
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 058823/0351 →
Change of Name
Feb 14, 2022
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 059085/0667 →
Confirmatory License
Feb 2, 2023
From: WOLFSPEED, INC.
To: U.S. DEPARTMENT OF ENERGY
Reel/Frame 062570/0755 →
Assignment of Assignor's Interest
Apr 25, 2023
From: DONOFRIO, MATTHEW; EDMOND, JOHN; GOLAKIA, HARSHAD
To: CREE, INC.
Reel/Frame 063424/0358 →
Security Interest
Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
Notice of Grant of Security Interest in Intellectual Property
Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
Notice of Grant of Security Interest in Intellectual Property
Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →