Method and device of field effect transistor including a base shorted to a source region

1. Field effect transistor comprising

a source region ( 9 ),

a drain region laterally spaced from said source region ( 9 ) and of highly doped n-type,

a base layer ( 5 ) of highly doped p-type,

an n-type channel layer ( 11 ) of lower doping concentration extending laterally and overlying both said source region ( 9 ) and base layer ( 5 ) and interconnecting the source region ( 9 ) and the drain region for conducting a current between these layers in the on-state of the transistor,

said source region ( 9 ) having a portion overlapping said base layer ( 5 ), interposed between said base layer ( 5 ) and channel layer ( 11 ) and defining a vertical edge along said base layer ( 5 ), and

a gate ( 16 ) formed upon the n-type channel layer ( 11 ) which is self-aligned both laterally and perpendicularly with respect to the underlying source region ( 9 ) and base layer ( 5 ), with said gate ( 16 ) not overlapping said source region ( 9 ) and entirely overlapping said base layer ( 5 ), and

additionally comprising a dielectric layer ( 14 ) situated upon said channel layer ( 11 ) and above both said source ( 9 ) and drain regions and comprising an opening for receiving metal forming the gate ( 16 ) self-aligned both laterally and perpendicularly.

2. Method for producing a field effect transistor according to claim 1 and comprising

a source region ( 9 ), a drain region and a channel layer ( 11 ) interconnecting the source and drain region, which includes the step of

providing a sacrificial layer ( 4 ) on part of a semiconductor material ( 1 ) whose edge is used to define the edge of an implant, such as the source region ( 9 ), in the semiconductor material ( 1 ), wherein the edge ( 4 c ) of the sacrificial layer ( 4 ) is subsequently used to define the edge of the gate ( 16 ).

3. Method according to claim 2 , further comprising the step of growing a second sacrificial layer ( 7 ) of thickness (t) over the semiconductor material ( 1 ) and the first sacrificial layer ( 4 ) to define a second point ( 8 ) on the semiconductor material at a lateral distance (t) from the edge ( 4 c ) of the first sacrificial layer ( 4 ).

4. Method according to claim 3 , further comprising the step of anisotropically etching away the second sacrificial layer ( 7 ) except for the section adjacent to the edge ( 4 c ) of the first sacrificial layer ( 4 ).

5. Method according to claim 2 , wherein the source ( 9 ) and the drain regions are formed prior to the formation of the channel layer ( 11 ) and the gate is formed after the formation of the channel layer ( 11 ).

6. Method according to claim 5 , wherein the width of the gate is determined by the accurately controlled growth of non-sacrificial layers such as semiconductor of dielectric layers upon the channel layer ( 11 ).

7. Method according to claim 2 , wherein the first sacrificial layer ( 4 ) comprises an oxide; such as silicone oxide, a nitride; such as a silicon nitride, or polysilicon.

8. Method according to claim 3 , wherein the second sacrificial layer ( 7 ) comprises an oxide, such as silicon oxide, a nitride, such as silicon nitride, or polysilicon.

9. Method according to claim 2 , wherein the semiconductor material ( 1 ) comprises Silicon, Silicon Carbide, Gallium Arsenide or any other group III-V semiconductor.

10. Method according to claim 2 , wherein the edge of the first sacrificial layer ( 4 c ) defines the edge of a highly doped p-type base layer ( 5 ).

11. Method according to claim 10 , wherein Aluminium, Beryllium or Boron is used as the dopant for the highly doped p-type base layer ( 5 ) when silicon carbide is used as the semiconductor material.

12. Method according to claim 11 , wherein the highly doped p-type base layer ( 5 ) is doped to a concentration of greater than 10 18 cm −3 when silicon carbide is used as the semiconductor material ( 1 ).

13. Method according to claim 8 , wherein a highly doped p-type base layer ( 5 ) is formed to totally overlap the gate ( 16 ).

14. Field effect transistor according to claim 1 , further comprising a highly doped p-type base layer arranged next to and under the channel layer at least partially overlapping the gate ( 16 ) arranged above the channel layer ( 11 ), said base layer being shorted to the source region.

15. Device comprising at least one field effect transistor according to claim 1 .

16. Use of a transistor according to claim 1 for switching high frequencies above 1 MHz, preferably above 1 GHz.

17. Use of a transistor according to claim 1 for switching high frequency signals with a power above 1 W.

18. Use of a transistor according to claim 1 in base stations for mobile telephones, radars, microwave heating applications, or for generating gas plasmas.

19. Method according to claim 2 , wherein the source ( 9 ) and the drain regions are formed prior to the formation of the channel layer ( 11 ) and the gate is formed after the formation of the channel layer ( 11 ).

20. Method according to claim 4 , wherein the source ( 9 ) and the drain regions are formed prior to the formation of the channel layer ( 11 ) and the gate is formed after the formation of the channel layer ( 11 ).

21. Transistor according to claim 1 , having just a single dielectric layer ( 14 ) situated upon said channel layer ( 11 ).

22. Transistor according to claim 1 , additionally comprising a thermal oxide layer ( 12 ) situated between said dielectric ( 14 ) and channel ( 11 ) layers and on either side of said gate ( 16 ).

23. Transistor according to claim 1 , wherein a vertical edge of said gate ( 16 ) and a vertical edge between said source region ( 9 ) and base layer ( 5 ) are situated in substantially the same vertical plane.

24. Transistor according to claim 23 , wherein said gate ( 16 ) is situated directly upon said channel layer ( 11 ).

25. Transistor according to claim 1 , wherein said gate ( 16 ) is situated directly upon said channel layer ( 11 ).