Heterojunction transistors including energy barriers
View Patent ↗A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.
1. A heterojunction transistor comprising:
a channel layer comprising a Group III nitride;
a barrier layer comprising a Group III nitride adjacent the channel layer wherein the barrier layer has a bandgap greater than a bandgap of the channel layer;
an energy barrier comprising a layer of a Group III nitride including indium adjacent the channel layer such that the channel layer is between the barrier layer and the energy barrier wherein the energy barrier has a narrower bandgap than the channel layer; and
a hole source layer comprising a Group III nitride adjacent the energy barrier such that the energy barrier is between the channel layer and the hole source layer and a hole source region is induced at an interface between the hole source layer and the energy barrier.
2. A heterojunction transistor according to claim 1 wherein the channel layer and the barrier layer cooperatively induce a two-dimensional electron gas at an interface between the channel layer and the barrier layer.
3. A heterojunction transistor according to claim 1 wherein the energy barrier comprises a layer of In x Ga 1-x N (0<x≦1).
4. A heterojunction transistor according to claim 3 wherein the energy barrier comprises a layer of InN.
5. A heterojunction transistor according to claim 3 wherein the energy barrier comprises a layer of In x Ga 1-x N (0<x<1).
6. A heterojunction transistor according to claim 5 wherein a mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier is at least about 1%.
7. A heterojunction transistor according to claim 6 wherein a mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier is in the range of about 1% to about 50%.
8. A heterojunction transistor according to claim 7 wherein a mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier is in the range of about 4% to about 16%.
9. A heterojunction transistor according to claim 1 wherein the energy barrier opposes movement of carriers away from the channel layer.
10. A heterojunction transistor according to claim 1 wherein the energy barrier comprises a quantum well.
11. A heterojunction transistor according to claim 1 further comprising:
source, drain, and gate contacts adjacent the barrier layer such that the barrier layer is between the channel layer and the source, drain, and gate contacts; and
a substrate adjacent the energy barrier such that the energy barrier is between the substrate and the channel layer.
12. A heterojunction transistor according to claim 1 wherein the barrier layer has a thickness in the range of about 0.1 nm to about 10 nm.
13. A heterojunction transistor according to claim 1 wherein the barrier layer and the energy barrier are separated by a distance in the range of about 5 nm to about 30 nm.
14. A heterojunction transistor according to claim 1 wherein the channel layer comprises a layer of Al y Ga 1-y N (0≦y<1), the barrier layer comprises a layer of Al z Ga 1-z N (0<z≦1), and y and z are different.
15. A heterojunction transistor according to claim 1 wherein a concentration of Al in the barrier layer is greater than a concentration of Al in the channel layer.
16. A heterojunction transistor comprising:
a channel layer;
a barrier layer adjacent the channel layer wherein the barrier layer and the channel layer cooperatively induce a two-dimensional electron gas at an interface between the channel layer and the barrier layer;
an energy barrier adjacent the channel layer such that the channel layer is between the barrier layer and the energy barrier wherein the energy barrier opposes movement of carriers away from the channel layer wherein the energy barrier has a narrower bandgap than the channel layer; and
a hole source layer adjacent the enemy barrier such that the energy barrier is between the channel layer and the hole source layer wherein a hole source region is induced at an interface between the hole source layer and the energy barrier.
17. A heterojunction transistor according to claim 16 wherein the channel layer comprises a first layer of a Group III nitride, wherein the barrier layer comprises a second layer of a Group III nitride, and wherein the energy barrier comprises a third layer of a Group III nitride.
18. A heterojunction transistor according to claim 16 wherein the energy barrier comprises a quantum well.
19. A heterojunction transistor according to claim 16 wherein the energy barrier comprises a layer of In x Ga 1-x N (0<x≦1).
20. A heterojunction transistor according to claim 19 wherein the energy barrier comprises a layer of InN.
21. A heterojunction transistor according to claim 19 wherein the energy barrier comprises a layer of In x Ga 1-x N (0<x<1).
22. A heterojunction transistor according to claim 21 wherein a mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier is at least about 1%.
23. A heterojunction transistor according to claim 22 wherein a mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier is in the range of about 1% to about 50%.
24. A heterojunction transistor according to claim 23 wherein a mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier is in the range of about 4% to about 16%.
25. A heterojunction transistor according to claim 16 wherein the energy barrier has a thickness in the range of no more than about 50 Angstroms.
26. A heterojunction transistor according to claim 16 further comprising:
source, drain, and gate contacts adjacent the barrier layer such that the barrier layer is between the channel layer and the source, drain, and gate contacts; and
a substrate adjacent the energy barrier such that the energy barrier is between the substrate and the channel layer.
27. A heterojunction transistor according to claim 16 wherein the channel layer comprises a Group III nitride, wherein the barrier comprises a Group III nitride, and wherein the barrier layer has a bandgap greater than a bandgap of the channel layer.
28. A heterojunction transistor according to claim 16 wherein the channel layer comprises a layer of Al y Ga 1-y N (0≦y<1), the barrier layer comprises a layer of Al z Ga 1-z N (0<z≦1), and y and z are different.
29. A heterojunction transistor according to claim 16 further comprising:
a cap layer comprising a Group III nitride adjacent the barrier layer such that the barrier layer is between the cap layer and the channel layer, wherein a concentration of Ga in the cap layer is greater than a concentration of Ga in the barrier layer.
30. A heterojunction transistor according to claim 16 wherein the barrier layer comprises a Group III nitride and the channel layer comprises a Group III nitride, and wherein a concentration of Al in the barrier layer is greater than a concentration of Al in the channel layer.
31. A heterojunction transistor according to claim 1 wherein the energy barrier has a thickness of no more than about 50 Angstroms.
32. A heterojunction transistor according to claim 1 further comprising:
a cap layer comprising a Group III nitride adjacent the barrier layer such that the barrier layer is between the cap layer and the channel layer, wherein a concentration of Ga in the cap layer is greater than a concentration of Ga in the barrier layer.
33. A heterojunction transistor according to claim 1 wherein the hole source layer has a higher bandgap than the energy barrier.
34. A heterojunction transistor according to claim 1 wherein the hole source layer is undoped.
35. A heterojunction transistor according to claim 1 wherein the hole source layer is doped with p-type dopants.
36. A heterojunction transistor according to claim 1 wherein the energy barrier has a first conductivity type and the hole source layer has a second conductivity type opposite the first conductivity type.
37. A heterojunction transistor according to claim 16 wherein the hole source layer has a higher bandgap than the energy barrier.
38. A heterojunction transistor according to claim 16 wherein the hole source layer is undoped.
39. A heterojunction transistor according to claim 16 wherein the hole source layer is doped with p-type dopants.
40. A heterojunction transistor according to claim 16 wherein the energy barrier has a first conductivity type and the hole source layer has a second conductivity type opposite the first conductivity type.
41. A heterojunction transistor according to claim 1 wherein a concentration of indium (In) in the energy barrier is greater than a concentration of indium (In) in the channel layer.
42. A heterojunction transistor according to claim 41 wherein the channel layer comprises a layer of Al y Ga 1-y N (0≦y<1).
43. A heterojunction transistor according to claim 1 wherein the energy barrier has a larger lattice constant than the channel layer.
44. A heterojunction transistor according to claim 16 wherein the energy barrier has a larger lattice constant than the channel layer.