Vertical JFET limited silicon carbide metal-oxide semiconductor field effect transistors

1. A silicon carbide metal-oxide semiconductor field effect transistor comprising:

a silicon carbide drift layer of a first conductivity type;

spaced apart silicon carbide well regions of a second conductivity type adjacent the drift layer; and

a silicon carbide region of the first conductivity type disposed between the well regions and the drift layer, the silicon carbide region of the first conductivity a first portion laterally extending along respective floors of the well regions and a second portion extending along respective sidewalls of the well regions, wherein the first portion has a higher carrier concentration than the second portion.

2. The transistor of claim 1 , wherein the second portion has have a higher carrier concentration than the drift layer.

3. The transistor of claim 1 , wherein the silicon carbide region of the first conductivity type has a thickness of about 0.5 μm to about 1.5 μm, and a carrier concentration of about 1×10 15 to about 5×10 17 cm −3 .

4. The transistor of claim 1 , wherein the silicon carbide region of the first conductivity type comprises an epitaxial layer of silicon carbide on the drift layer.

5. The transistor of claim 4 , wherein the well regions are disposed in but not through the epitaxial layer of silicon carbide.

6. The transistor of claim 1 , wherein the first conductivity type is n-type, and wherein the second conductivity type is p-type.

7. The transistor of claim 6 , wherein the silicon carbide region of the first conductivity type comprises an implanted n-type region in the drift layer.

8. The transistor of claim 6 , wherein the p-type well regions comprise aluminum implanted regions in the drift layer.

9. The transistor of claim 6 , further comprising:

respective n-type silicon carbide regions within the p-type silicon carbide well regions.

10. The transistor of claim 9 , further comprising:

an oxide layer on the drift layer, the well regions, and the respective n-type silicon carbide regions;

a gate contact on the oxide layer;

source contacts on the respective n-type silicon carbide regions at opposite sides of the oxide layer; and

a drain contact under the drift layer and opposite the oxide layer.

11. The transistor of claim 10 , further comprising:

an n-type epitaxial layer on the well regions and on portions of the respective n-type silicon carbide regions within the well regions, wherein the n-type epitaxial layer is disposed between the well regions and the oxide layer.

12. The transistor of claim 10 , wherein the gate contact comprises polysilicon or metal.

13. The transistor of claim 10 , further comprising an n-type silicon carbide substrate disposed between the drift layer and the drain contact.

14. The transistor of claim 10 , further comprising:

respective p-type silicon carbide regions disposed within the well regions and adjacent the respective n-type silicon carbide regions,

wherein the source contacts extend on the respective p-type silicon carbide regions.

15. A silicon carbide metal-oxide semiconductor field effect transistor, comprising:

an n-type silicon carbide drift layer;

a first p-type silicon carbide region on the drift layer;

a first n-type silicon carbide region within the first p-type silicon carbide region; and

a second n-type silicon carbide region disposed between the first p-type silicon carbide region and the drift layer, the second n-type silicon carbide region comprising a lateral portion extending beneath the first p-type silicon carbide region and a vertical portion extending along a sidewall of the first p-type silicon carbide region, wherein a carrier concentration of the vertical portion is lower than a carrier concentration of the lateral portion.

16. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 15 , wherein the carrier concentration of the vertical portion is higher than the carrier concentration of the drift layer.

17. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 15 , further comprising:

an n-type epitaxial layer on the first p-type silicon carbide region and a portion of the first n-type region, and disposed between the first p-type silicon carbide region and the oxide layer.

18. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 15 , further comprising:

an oxide layer on the drift layer, the first p-type silicon carbide region, and the first n-type silicon carbide region;

a gate contact on the oxide layer;

a source contact on the first n-type silicon carbide region; and

a drain contact under the drift layer and opposite the oxide layer.

19. A silicon carbide metal-oxide semiconductor field effect transistor of claim 15 , wherein the first p-type silicon carbide region comprises a silicon carbide region implanted with aluminum.

20. A silicon carbide metal-oxide semiconductor filed effect transistor according to claim 19 , wherein the second n-type silicon carbide region comprises an implanted n-type region, in the drift layer, wherein a depth of the first p-type silicon carbide region is less than a depth of the second n-type silicon carbide region.

21. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 19 , wherein the second n-type silicon carbide region comprises an epitaxial layer of silicon carbide on the drift layer, and wherein the first p-type silicon carbide region is disposed in but not through the epitaxial layer of silicon carbide.