Low profile, highly configurable, current sharing paralleled wide band gap power device power module
View Patent ↗A power module with multiple equalized parallel power paths supporting multiple parallel bare die power devices constructed with low inductance equalized current paths for even current sharing and clean switching events. Wide low profile power contacts provide low inductance, short current paths, and large conductor cross section area provides for massive current carrying. An internal gate & source kelvin interconnection substrate is provided with individual ballast resistors and simple bolted construction. Gate drive connectors are provided on either left or right size of the module. The module is configurable as half bridge, full bridge, common source, and common drain topologies.
1. A power module apparatus, comprising:
a base plate defining a topology pattern;
a power substrate positioned above the base plate;
at least two power contacts, each of the at least two power contacts electrically connected to the power substrate;
at least two parallel shared current path power devices electrically connected to the at least two power contacts;
a gate and source board mounted above the power substrate, the gate and source board including a first interconnection channel and a second interconnection channel, each interconnection channel mounted in an interconnection position selected from a position group, the position group consisting of a first interconnection position, a second interconnection position, a third interconnection position, and a fourth interconnection position;
gate drive connectors electrically connected to the gate and source board;
a housing secured to the power substrate, the gate drive connectors and the at least two power contacts extending through the housing, the housing defining fastener apertures;
fasteners positioned in the fastener apertures; and
the at least two power contacts bent over the fastener apertures to retain the fasteners in the fastener apertures.
2. The apparatus of claim 1 ,
wherein the topology pattern forms a half bridge substrate.
3. The apparatus of claim 2 , wherein:
the first interconnection channel is mounted in the first interconnection position; and
the second interconnection channel is mounted in the third interconnection position.
4. The apparatus of claim 2 , wherein:
the first interconnection channel is mounted in the second interconnection position; and
the second interconnection channel is mounted in the third interconnection position.
5. The apparatus of claim 1 ,
wherein the topology pattern forms a common source substrate.
6. The apparatus of claim 5 , wherein:
the first interconnection channel is mounted in the first interconnection position; and
the second interconnection channel is mounted in the fourth interconnection position.
7. The apparatus of claim 1 ,
wherein the topology pattern forms a common drain substrate.
8. The apparatus of claim 1 ,
wherein the at least two parallel shared current path power devices include a first paralleled power device, a second paralleled power device, and a third paralleled power device.
9. The apparatus of claim 8 ,
wherein the at least two parallel shared current path power devices include a fourth paralleled power device.
10. The apparatus of claim 9 ,
wherein the at least two parallel shared current path power devices include a fifth paralleled power device, and a sixth paralleled power device.
11. The apparatus of claim 10 ,
wherein the at least two parallel shared current path power devices include a seventh paralleled power device, and an eight paralleled power device.
12. The apparatus of claim 11 ,
wherein the at least two parallel shared current path power devices include a ninth paralleled power device, and a tenth paralleled power device.
13. The apparatus of claim 12 ,
wherein the at least two parallel shared current path power devices include an eleventh paralleled power device.
14. The apparatus of claim 1 ,
wherein the housing defines passivation entries and vents.
15. The apparatus of claim 1 ,
wherein the housing defines a power contact pinch and radius for receiving and bending one of the at least two power contacts.
16. A gate and source board apparatus for use with multiple power die positioned in parallel, the apparatus comprising:
a track paralleling the multiple power die;
at least two gate bond pads positioned parallel to the track; and
individual ballast resistors selectively connecting each of the at least two gate bond pads to the track.
17. The apparatus of claim 16 ,
wherein the track is a gate track.
18. The apparatus of claim 17 ,
wherein the track is a source track.