Patent Assignment
Reel/Frame 072992/0588
Notice of Grant of Security Interest in Intellectual Property
Recorded: 2025-09-30
Pages: 73
Assignor
WOLFSPEED, INC.
Executed: 2025-09-29
Assignee
U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
333 COMMERCE STREET, SUITE 900, NASHVILLE, TENNESSEE, 37201
Covered Properties
(769)
Multi-Chamber Mocvd Growth Apparatus for High Performance/High Throughput
Reduction of Subsurface Damage in the Production of Bulk Sic Crystals
Transistors Having Buried N-Type and P-Type Regions Beneath the Source Region
Transistors Having Buried N-Type and P-Type Regions Beneath the Source Region and Methods of Fabricating the Same
Apparatus and Method for the Production of Bulk Silicon Carbide Single Crystals
Methods of Fabricating Silicon Nitride Regions in Silicon Carbide and Resulting Structures
Devices Having Thick Semi-Insulating Epitaxial Gallium Nitride Layer
Composite Substrates of Conductive and Insulating or Semi-Insulating Group Iii-Nitrides for Group Iii-Nitride Devices
Binary Group Iii-Nitride Based High Electron Mobility Transistors
Silicon carbide junction barrier schottky diodes with supressed minority carrier injection
Method and Apparatus for the Production of Silicon Carbide Crystals
High Voltage Silicon Carbide Devices Having Bi-Directional Blocking Capabilities
Methods of Fabricating Silicon Carbide Devices Having Smooth Channels
Fluid-Dispensing Apparatus with Controlled Tear-Off
Method of Manufacturing Gallium Nitride Based High-Electron Mobility Devices
Semiconductor Devices Having Varying Electrode Widths to Provide Non-Uniform Gate Pitches and Related Methods
High Voltage Silicon Carbide Devices Having Bi-Directional Blocking Capabilities
Low dislocation density group III nitride layers on silicon carbide substrates and methods of making the same
Semiconductor Device Comprising a Junction Having a Plurality of Rings
Methods, Apparatus and Computer Program Products for Controlling a Volume of Liquid in Semiconductor Processing Based on Reflected Optical Radiation
Double Side Polished Wafer Scratch Inspection Tool
Directed Reagents to Improve Material Uniformity
Gas driven rotation apparatus and method for forming crystalline layers
Silicon Carbide Bipolar Junction Transistors Having Epitaxial Base Regions and Multilayer Emitters and Methods of Fabricating the Same
Methods of Fabricating Oxide Layers on Silicon Carbide Layers Utilizing Atomic Oxygen
Restricted Radiated Heating Assembly for High Temperature Processing
Semiconductor Devices Including Implanted Regions and Protective Layers and Methods of Forming the Same
Silicon Carbide Bipolar Junction Transistors Having a Silicon Carbide Passivation Layer on the Base Region Thereof
Environmentally Robust Passivation Structures for High-Voltage Silicon Carbide Semiconductor Devices
Methods of Fabricating Transistors Including Supported Gate Electrodes
Dispensed Electrical Interconnections
High power silicon carbide (SiC) PiN diodes having low forward voltage drops
Optically Triggered Wide Bandgap Bipolar Power Switching Devices and Circuits
One Hundred Millimeter SiC Crystal Grown on Off-Axis Seed
Method of Fabricating Seminconductor Devices Including Self Aligned Refractory Contacts
Methods for Fabricating Semiconductor Devices Having Reduced Implant Contamination
Methods for Reducing Contamination of Semiconductor Devices and Materials During Wafer Processing
High-Temperature Ion Implantation Apparatus and Methods of Fabricating Semiconductor Devices Using High-Temperature Ion Implantation
Semiconductor Device
Reduced Leakage Power Devices by Inversion Layer Surface Passivation
Structure and Method for Reducing Forward Voltage Across a Silicon Carbide-Group Iii Nitride Interface
Heat Sink Assembly and Related Methods for Semiconductor Vacuum Processing Systems
Robust Transistors with Fluorine Treatment
Methods of Forming Sic Mosfets with High Inversion Layer Mobility
Methods of Fabricating Transistors Including Dielectrically-Supported Gate Electrodes
Semiconductor Devices Including Schottky Diodes with Controlled Breakdown
Transistors Having Buried P-Type Layers Coupled to the Gate
Integrated Circuit Esd Protection
Methods and Apparatus for Reducing Buildup of Deposits in Semiconductor Processing Equipment
Power Switching Semiconductor Devices Including Rectifying Junction-Shunts
Semiconductor Devices Including Implanted Regions for Providing Low-Resistance Contact to Buried Layers and Related Devices
High Voltage Gan Transistors
Epitaxial Semiconductor Structures Having Reduced Stacking Fault Nucleation Sites
Silicon Carbide Dimpled Substrate
Low Voltage Diode with Reduced Parasitic Resistance and Method for Fabricating
Schottky Diode Structure with Silicon Mesa and Junction Barrier Schottky Wells
Diode Having Reduced on-Resistance and Associated Method of Manufacture
Transistors Having Implanted Channels and Implanted P-Type Regions Beneath the Source Region
Insulated Gate Bipolar Transistors Including Current Suppressing Layers
Silicon Carbide Self-Aligned Epitaxial Mosfet for High Powered Device Applications
Nitride Semiconductor Structures with Interlayer Structures
Thick Nitride Semiconductor Structures with Interlayer Structures
High Temperature Performance Capable Gallium Nitride Transistor
Methods of Forming Silicon Carbide Switching Devices Including P-Type Channels
Silicon Carbide Power Devices Including P-Type Epitaxial Layers and Direct Ohmic Contacts
Methods of Forming Ohmic Layers Through Ablation Capping Layers
High Power Insulated Gate Bipolar Transistors
Polytype Hetero-Interface High Electron Mobility Device and Method of Making
Passivation of Wide Band-Gap Based Semiconductor Devices with Hydrogen-Free Sputtered Nitrides
Halogen Assisted Physical Vapor Transport Method for Silicon Carbide Growth
High Temperature Ion Implantation of Nitride Based Hemts
Grid-Umosfet with Electric Field Shielding of Gate Oxide
Insulated Gate Bipolar Conduction Transistors (Ibcts) and Related Methods of Fabrication
Selective Wet Etching of Gold-Tin Based Solder
Gan Based Hemts with Buried Field Plates
Transistors and Method for Making Ohmic Contact to Transistors
Short Gate High Power Mosfet and Method of Manufacture
Transistor with a-Face Conductive Channel and Trench Protecting Well Region
Metallization structure for high power microelectronic devices
Pendeo Epitaxial Structures and Devices
Semiconductor Transistor with P Type Re-Grown Channel Layer
Methods of Forming Group Iii-Nitride Semiconductor Devices Including Implanting Ions Directly into Source and Drain Regions and Annealing to Activate the Implanted Ions
Junction Barrier Schottky Diodes with Current Surge Capability
Normally-Off Semiconductor Devices
Semiconductor Devices Including Implanted Regions and Protective Layers
Mesa Termination Structures for Power Semiconductor Devices Including Mesa Step Buffers
Power Semiconductor Devices with Mesa Structures and Buffer Layers Including Mesa Steps
Printed Circuit Board for Harsh Environments
Bidirectional Silicon Carbide Transient Voltage Suppression Devices
Rectifier with Sic Bipolar Junction Transistor Rectifying Elements
Methods of Forming Semiconductor Devices Including Epitaxial Layers and Related Structures
High-Temperature Ion Implantation Apparatus and Methods of Fabricating Semiconductor Devices Using High-Temperature Ion Implantation
Wide Bandgap Bipolar Turn-Off Thyristor Having Non-Negative Temperature Coefficient and Related Control Circuits
Schottky Diodes Containing High Barrier Metal Islands in a Low Barrier Metal Layer and Methods of Forming the Same
Transistors Including Supported Gate Electrodes
Schottky Diodes Including Polysilicon Having Low Barrier Heights and Methods of Fabricating the Same
Semiconductor Devices Including Schottky Diodes Having Doped Regions Arranged as Islands and Methods of Fabricating Same
Methods of Fabricating Oxide Layers on Silicon Carbide Layers Utilizing Atomic Oxygen
High-Gain Wide Bandgap Darlington Transistors and Related Methods of Fabrication
High Breakdown Voltage Wide Band-Gap Mos-Gated Bipolar Junction Transistors with Avalanche Capability
High Speed Rectifier Circuit
Semiconductor Devices Including Electrodes with Integrated Resistances
Semiconductor Devices with Current Shifting Regions and Related Methods
Transistors with a Gate Insulation Layer Having a Channel Depleting Interfacial Charge and Related Fabrication Methods
Solid-State Pinch Off Thyristor Circuits
Electronic Device Submounts with Thermally Conductive Vias and Light Emitting Devices Including the Same
High Voltage Insulated Gate Bipolar Transistors with Minority Carrier Diverter
Methods of Forming Power Switching Semiconductor Devices Including Rectifying Junction-Shunts
Transistors with Semiconductor Interconnection Layers and Semiconductor Channel Layers of Different Semiconductor Materials
Methods of Fabricating Transistors Using Laser Annealing of Source/Drain Regions
Robust Transistors with Fluorine Treatment
Low-Loss Noise-Resistant High-Temperature Gate Driver Circuits
Patent:
7,965,522 →
Application:
12/586,729 →
Method of Manufacturing Silicon Carbide Self-Aligned Epitaxial Mosfet for High Powered Device Applications
Monolithic High Voltage Switching Devices
Power Switching Devices Having Controllable Surge Current Capabilities
Power Semiconductor Devices Having Selectively Doped Jfet Regions and Related Methods of Forming Such Devices
Devices with Crack Stops
Stable Power Devices on Low-Angle Off-Cut Silicon Carbide Crystals
Methods of Fabricating Transistors Having Buried P-Type Layers Coupled to the Gate
High Voltage Gan Transistors
Semiconductor Device Structures with Modulated Doping and Related Methods
Restricted Radiated Heating Assembly for High Temperature Processing
Growing Polygonal Carbon from Photoresist
Methods of Forming Contact Structures Including Alternating Metal and Silicon Layers and Related Devices
Semiconductor Devices with Heterojunction Barrier Regions and Methods of Fabricating Same
Diffused Junction Termination Structures for Silicon Carbide Devices and Methods of Fabricating Silicon Carbide Devices Incorporating Same
Methods of Fabricating Transistors Including Dielectrically-Supported Gate Electrodes and Related Devices
Multilayer Diffusion Barriers for Wide Bandgap Schottky Barrier Devices
Wide Band-Gap MOSFETs Having a Heterojunction Under Gate Trenches Thereof and Related Methods of Forming Such Devices
Method for Controlled Growth of Silicon Carbide and Structures Produced by Same
Semiconductor Devices Having Improved Adhesion and Methods of Fabricating the Same
Methods of Forming Sic Mosfets with High Inversion Layer Mobility
Semiconductor Devices Having Gates Including Oxidized Nickel
Smoothing Method for Semiconductor Material and Wafers Produced by Same
Power Converter Circuits Including High Electron Mobility Transistors for Switching and Rectifcation
Electronic Device Structure Including a Buffer Layer on a Base Layer
Electronic Device Structure with a Semiconductor Ledge Layer for Surface Passivation
Semiconductor Device Structures with Modulated and Delta Doping and Related Methods
Patent:
8,536,615 →
Application:
12/848,600 →
Circuit Breaker
Semiconductor Device with Protecting Film and Method of Fabricating the Semiconductor Device with Protecting Film
Methods of Forming Semiconductor Contacts
Multi-Rotation Epitaxial Growth Apparatus and Reactors Incorporating Same
Low Voltage Diode with Reduced Parasitic Resistance and Method for Fabricating
Methods of Fabricating Nitride Semiconductor Structures with Interlayer Structures
Normally-Off D-Mode Driven Direct Drive Cascode
Patent:
8,228,114 →
Application:
12/924,622 →
Contact Pad
Apparatus for Reducing Buildup of Deposits in Semiconductor Processing Equipment
High Voltage Gan Transistors
Silicon Carbide Switching Devices Including P-Type Channels
Semiconductor Device Having High Performance Channel
Semiconductor Devices Including Schottky Diodes Having Overlapping Doped Regions and Methods of Fabricating Same
Coupled Inductor Output Filter
Patent:
8,427,120 →
Application:
13/068,229 →
Recessed Termination Structures and Methods of Fabricating Electronic Devices Including Recessed Termination Structures
Sic Devices with High Blocking Voltage Terminated by a Negative Bevel
Robust Transistors with Fluorine Treatment
Thin Film Resistor
Transistor with a-Face Conductive Channel and Trench Protecting Well Region
Methods of Fabricating Normally-Off Semiconductor Devices
Ohmic Contact to Semiconductor Device
Ohmic Contact Structure for Group Iii Nitride Semiconductor Device Having Improved Surface Morphology and Well-Defined Edge Features
System and Method for Wafer Level Packaging
Forming Sic Mosfets with High Channel Mobility by Treating the Oxide Interface with Cesium Ions
Wet Chemistry Processes for Fabricating a Semiconductor Device with Increased Channel Mobility
Semiconductor Device with Increased Channel Mobility and Dry Chemistry Processes for Fabrication Thereof
Schottky Diode
Edge Termination Structure Employing Recesses for Edge Termination Elements
Schottky Diode Employing Recesses for Elements of Junction Barrier Array
Gan Based Hemts with Buried Field Plates
Power Switching Semiconductor Devices Including Rectifying Junction-Shunts
Bipolar Junction Transistor Structure for Reduced Current Crowding
Mesa Termination Structures for Power Semiconductor Devices and Methods of Forming Power Semiconductor Devices with Mesa Termination Structures
Sic Devices with High Blocking Voltage Terminated by a Negative Bevel
Semiconductor Device and Fabrication Method for the Same
High Voltage Semiconductor Devices Including Electric Arc Suppression Material and Methods of Forming the Same
Schottky Contact
Polymer via Plugs with High Thermal Integrity
Pcb Based Rf-Power Package Window Frame
Bipolar Junction Transistor with Improved Avalanche Capability
High Voltage Driver
High Voltage Gan Transistor
Optically Assist-Triggered Wide Bandgap Thyristors Having Positive Temperature Coefficients
High Temperature Performance Capable Gallium Nitride Transistor
Transistor with a-Face Conductive Channel and Trench Protecting Well Region
Normally-Off Semiconductor Devices
High Temperature Half Bridge Gate Driver
Voltage Regulator Circuitry Operable in a High Temperature Environment of a Turbine Engine
Junction Barrier Schottky Diodes with Current Surge Capability
Monolithic Bidirectional Silicon Carbide Switching Devices
Power Module for Supporting High Current Densities
Semiconductor Devices with Non-Implanted Barrier Regions and Methods of Fabricating Same
Semiconductor Devices Including Epitaxial Layers and Related Methods
Using a Carbon Vacancy Reduction Material to Increase Average Carrier Lifetime in a Silicon Carbide Semiconductor Device
Predisposed High Electron Mobility Transistor
Hydrogen Mitigation Schemes in the Passivation of Advanced Devices
Using Stress Reduction Barrier Sub-Layers in a Semiconductor Die
Increased Transition Speed Switching Device Driver
Ni-Rich Schottky Contact
Super Surge Diodes
Schottky Structure Employing Central Implants Between Junction Barrier Elements
Low Voltage Diode with Reduced Parasitic Resistance and Method for Fabricating
Devices with Crack Stops
Dielectric Solder Barrier for Semiconductor Devices
Transistor Structures Having a Deep Recessed P+ Junction and Methods for Making Same
Transistor Structures Having Reduced Electrical Field at the Gate Oxide and Methods for Making Same
Thick Nitride Semiconductor Structures with Interlayer Structures and Methods of Fabricating Thick Nitride Semiconductor Structures
Method for Controlled Growth of Silicon Carbide and Structures Produced by Same
Mix Doping of a Semi-Insulating Group Iii Nitride
Tunnel Junction Field Effect Transistors Having Self-Aligned Source and Gate Electrodes and Methods of Forming the Same
Floating Bond Pad for Power Semiconductor Devices
Field Effect Transistor Devices with Regrown P-Layers
Field Effect Transistor Devices with Protective Regions
Field Effect Transistor Devices with Buried Well Protection Regions
Gate Contact for a Semiconductor Device and Methods of Fabrication Thereof
Field Effect Transistor Devices with Buried Well Regions and Epitaxial Layers
Encapsulation of Advanced Devices Using Novel Pecvd and Ald Schemes
Wafer-Level Die Attach Metallization
Low Loss Electronic Devices Having Increased Doping for Reduced Resistance and Methods of Forming the Same
Grid-Umosfet with Electric Field Shielding of Gate Oxide
Bidirectional Silicon Carbide Transient Voltage Supression Devices
Smoothing Method for Semiconductor Material and Wafers Produced by Same
Autonomous Temperature Accelerometer Sensor
Patent:
9,435,819 →
Application:
13/872,505 →
Silver Filled Trench Substrate for High Power and/or High Temperature Electronics
Patent:
9,615,452 →
Application:
13/891,720 →
High Temperature Magnetic Amplifiers
Patent:
9,118,289 →
Application:
13/891,787 →
High Performance Power Module
Cascode Structures for Gan Hemts
Vertical Power Transistor with Built-in Gate Buffer
Recessed Field Plate Transistor Structures
Enhanced Gate Dielectric for a Field Effect Device with a Trenched Gate
Methods of Forming Junction Termination Extension Edge Terminations for High Power Semiconductor Devices and Related Semiconductor Devices
Edge Termination Technique for High Voltage Power Devices Having a Negative Feature for an Improved Edge Termination Structure
Low Profile High Temperature Double Sided Flip Chip Power Packaging
Patent:
9,275,938 →
Application:
14/016,728 →
CASCODE STRUCTURES WITH GaN CAP LAYERS
Monolithically Integrated Vertical Power Transistor and Bypass Diode
Semiconductor Device Including a Power Transistor Device and Bypass Diode
Layout Configurations for Integrating Schottky Contacts into a Power Transistor Device
Boost Converter with Reduced Switching Loss and Methods of Operating the Same
Devices Including Ultra-Short Gates and Methods of Forming Same
Thin Film Resistor
Field Effect Device with Enhanced Gate Dielectric Structure
Semiconductor Devices in Sic Using Vias Through N-Type Substrate for Backside Contact to P-Type Layer
High Temperature Equalized Electrical Parasitic Power Packaging Method for Many Paralleled Semiconductor Power Devices
Patent:
9,095,054 →
Application:
14/054,089 →
Method for Reworkable Packaging of High Speed, Low Electrical Parasitic Power Electronics Modules Through Gate Drive Integration
Patent:
9,407,251 →
Application:
14/100,288 →
Diffused Junction Termination Structures for Silicon Carbide Devices
Schottky Diode
Stress Mitigation for Thin and Thick Films Used in Semiconductor Circuitry
Apparatus Having Self Healing Liquid Phase Power Connects and Method Thereof
Patent:
9,728,868 →
Application:
14/176,494 →
Method of Manufacturing Precise Semiconductor Contacts
Power Conversion Electronics Having Conversion and Inverter Circuitry
Semiconductor Device with Self-Aligned Ohmic Contacts
Converter Circuitry
Igbt Structure for Wide Band-Gap Semiconductor Materials
Application:
14/212,991 →
Publication:
US 2015/0263145
Seminconductor Device with Spreading Layer
High Power Insulated Gate Bipolar Transistors
HIGH CURRENT, LOW SWITCHING LOSS SiC POWER MODULE
Controlled Ion Implantation Into Silicon Carbide Using Channeling And Devices Fabricated Using Controlled Ion Implantation Into Silicon Carbide Using Channeling
Over-Mold Packaging for Wide Band-Gap Semiconductor Devices
Methods of Forming Buried Junction Devices in Silicon Carbide Using Ion Implant Channeling and Silicon Carbide Devices Including Buried Junctions
Igbt with Bidirectional Conduction
Step Etched Metal Electrical Contacts
Patent:
9,967,977 →
Application:
14/308,283 →
Multi-Module, Scalable, High Power Density, Radiation-Hardened Power Converter Interface System
Patent:
9,419,448 →
Application:
14/308,308 →
Non Linear Resonant Switch Cell
Patent:
9,559,684 →
Application:
14/309,155 →
Electronic Device Structure with a Semiconductor Ledge Layer for Surface Passivation
Methods of Fabricating Semiconductor Devices Including Implanted Regions for Providing Low-Resistance Contact to Buried Layers and Related Devices
Transistors with a Gate Insulation Layer Having a Channel Depleting Interfacial Charge
Insulated Gate Bipolar Transistors Including Current Suppressing Layers
High Power Density, High Efficiency Power Electronic Converter
Semiconductor Devices with Heterojunction Barrier Regions and Methods of Fabricating Same
Power Converter Circuits Including High Electron Mobility Transistors for Switching and Rectification
High Voltage Power Chip Module
Semiconductor Device with Improved Field Plate
Semiconductor Device with Improved Field Plate
A Semiconductor Package Having a Baseplate with a Die Attach Region and a Peripheral Region
Semiconductor Device with Improved Insulated Gate
Monolithic Bidirectional Silicon Carbide Switching Devices
Pecvd Protective Layers for Semiconductor Devices
Power Semiconductor Devices Having Superjunction Structures with Implanted Sidewalls
Wafer-Level Die Attach Metallization
Gate Contact for a Semiconductor Device and Methods of Fabrication Thereof
Low Profile, Highly Configurable, Current Sharing Paralleled Wide Band Gap Power Device Power Module
Active Energy Recovery Clamping Circuit to Improve the Performance of Power Converters
Patent:
9,647,563 →
Application:
14/634,252 →
Multi-Cavity Package Having Single Metal Flange
Hybrid Analog and Digital Power Converter Controller
High Voltage Gan Transistor
Surface Mount Device with Stress Mitigation Measures
Patent:
9,450,163 →
Application:
14/721,525 →
Schottky Diode
Field Effect Transistor Devices with Buried Well Protection Regions
High Voltage Power Module
Optically Assist-Triggered Wide Bandgap Thyristors Having Positive Temperature Coefficients
Method and Device for a High Temperature Vacuum-Safe Solder Stop Utilizing Laser Processing of Solderable Surfaces for an Electronic Module Assembly
Tunnel Junction Field Effect Transistors Having Self-Aligned Source and Gate Electrodes and Methods of Forming the Same
High Speed, Efficient Sic Power Module
High Current, Low Switching Loss Sic Power Module
Schottky Structure Employing Central Implants Between Junction Barrier Elements
Vertical Power Transistor Device
Super Junction Power Semiconductor Devices Formed via Ion Implantation Channeling Techniques and Related Methods
Gallium Nitride High-Electron Mobility Transistors with P-Type Layers and Process for Making the Same
Low Profile, Highly Configurable, Current Sharing Paralleled Wide Band Gap Power Device Power Module
High Speed, Efficient Sic Power Module
Methods of Forming Power Semiconductor Devices Having Superjunction Structures with Pillars Having Implanted Sidewalls
Methods of Forming Buried Junction Devices in Silicon Carbide Using Ion Implant Channeling and Silicon Carbide Devices Including Buried Junctions
Transistor Structures Having Reduced Electrical Field at the Gate Oxide and Methods for Making Same
Power Schottky Diodes Having Local Current Spreading Layers and Methods of Forming Such Devices
Patent:
9,929,284 →
Application:
15/349,092 →
Ohmic Contact Structure for Group Iii Nitride Semiconductor Device Having Improved Surface Morphology and Well-Defined Edge Features
Power Semiconductor Devices Having Gate Trenches and Buried Edge Terminations and Related Methods
Power Semiconductor Devices Having Gate Trenches with Implanted Sidewalls and Related Methods
Patent:
9,887,287 →
Application:
15/372,516 →
Field Effect Transistor Devices with Buried Well Protection Regions
Power Modules Having an Integrated Clamp Circuit and Process Thereof
Stabilized, High-Doped Silicon Carbide
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Vertical Fet Structure
Gallium Nitride High-Electron Mobility Transistors with Deep Implanted P-Type Layers in Silicon Carbide Substrates for Power Switching and Radio Frequency Applications and Process for Making the Same
Power Modules Having an Integrated Clamp Circuit and Process Thereof
Power Module Having a Switch Module for Supporting High Current Densities
Low Switching Loss High Performance Power Module
Power Module with Improved Reliability
Patent:
9,998,109 →
Application:
15/594,868 →
Depletion Mode Semiconductor Devices Including Current Dependent Resistance
Power Schottky Diodes Having Closely-Spaced Deep Blocking Junctions in a Heavily-Doped Drift Region
Die-Attach Method to Compensate for Thermal Expansion
Power Switching Devices with Dv/Dt Capability and Methods of Making Such Devices
Controlled Ion Implantation into Silicon Carbide Using Channeling and Devices Fabricated Using Controlled Ion Implantation into Silicon Carbide Using Channeling
Totem Pole Pfc Converter and System
Patent:
10,224,809 →
Application:
15/725,324 →
Rivetless Lead Fastening for a Semiconductor Package
High Voltage Power Module
Semiconductor Die with Improved Ruggedness
Vertical Semiconductor Device with Improved Ruggedness
Power Silicon Carbide Based Mosfet Transistors with Improved Short Circuit Capabilities and Methods of Making Such Devices
Silicon Carbide Power Module
Vertical Power Transistor Device
Patent:
48,380 →
Application:
15/970,148 →
Power Module with Improved Reliability
Wide Bandgap Semiconductor Device
Method and Device for a High Temperature Vacuum-Safe Solder Resist Utilizing Laser Ablation of Solderable Surfaces for an Electronic Module Assembly
Transistor Structures Having a Deep Recessed P+ Junction and Methods for Making Same
Power Module for Supporting High Current Densities
Field Effect Transistor Devices with Buried Well Protection Regions
High Electron Mobility Transistors Having Improved Drain Current Drift and/or Leakage Current Performance
Gallium Nitride High-Electron Mobility Transistors with Deep Implanted P-Type Layers in Silicon Carbide Substrates for Power Switching and Radio Frequency Applications and Process for Making the Same
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Methods and Apparatuses Related to Shaping Wafers Fabricated by Ion Implantation
Carrier-Assisted Method for Parting Crystalline Material Along Laser Damage Region
Laser-Assisted Method for Parting Crystalline Material
Patent:
10,576,585 →
Application:
16/274,064 →
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Power Semiconductor Devices Having Top-Side Metallization Structures That Include Buried Grain Stop Layers
Structures for Reducing Electron Concentration and Process for Reducing Electron Concentration
High Voltage Power Module
Group Iii-Nitride High-Electron Mobility Transistors with Buried P-Type Layers and Process for Making the Same
Transistor Semiconductor Die with Increased Active Area
Semiconductor Die with Improved Ruggedness
Laser-Assisted Method for Parting Crystalline Material
Patent:
10,562,130 →
Application:
16/410,487 →
Power Semiconductor Devices Having Reflowed Inter-Metal Dielectric Layers
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
Patent:
10,611,052 →
Application:
16/415,721 →
High Reliability Semiconductor Devices and Methods of Fabricating the Same
Methods for Dicing Semiconductor Wafers and Semiconductor Devices Made by the Methods
High Electron Mobility Transistors Having Improved Contact Spacing and/or Improved Contact Vias
Package for Power Electronics
Device Design for Short-Circuitry Protection Circuitry Within Transistors
Composite-Channel High Electron Mobility Transistor
Depletion Mode Semiconductor Devices Including Current Dependent Resistance
Hybrid Power Module
Overcurrent Protection for Power Transistors
Power Silicon Carbide Based Mosfet Transistors with Improved Short Circuit Capabilities and Methods of Making Such Devices
Contact and Die Attach Metallization for Silicon Carbide Based Devices and Related Methods of Sputtering Eutectic Alloys
Multi-Cavity Package Having Single Metal Flange
Systems and Processes for Increasing Semiconductor Device Reliability
Semiconductor Device with Improved Short Circuit Withstand Time and Methods for Manufacturing the Same
Stepped Field Plates with Proximity to Conduction Channel and Related Fabrication Methods
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Passivation Structure for Semiconductor Devices
Patent:
49,167 →
Application:
16/681,044 →
Semiconductors with Improved Thermal Budget and Process of Making Semiconductors with Improved Thermal Budget
Semiconductors Having Die Pads with Environmental Protection and Process of Making Semiconductors Having Die Pads with Environmental Protection
Application:
16/704,644 →
Publication:
US 2021/0175138
Methods and Systems for Matching Both Dynamic and Static Parameters in Dies, Discretes, and/or Modules, and Methods and Systems Based on the Same
Nondestructive Characterization for Crystalline Wafers
Stabilized, High-Doped Silicon Carbide
Dislocation Distribution for Silicon Carbide Crystalline Materials
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
High Speed, Efficient Sic Power Module
Laser-Assisted Method for Parting Crystalline Material
Patent:
11,219,966 →
Application:
16/792,261 →
Vertical Semiconductor Device with Improved Ruggedness
Alignment for Wafer Images
Semiconductor Die Having a Drift Region with a Charge Compensation Region Formed Therein Where the Charge Compensation Region Has a Plurality of Guard Rings Formed in First and Second Opposite Doping Type Portions
Application:
16/806,489 →
Publication:
US 2021/0273090
System and Process for Implementing Accelerated Test Conditions for High Voltage Lifetime Evaluation of Semiconductor Power Devices
Power Switching Devices with High Dv/Dt Capability and Methods of Making Such Devices
Power Semiconductor Package with Improved Performance
High Speed, Efficient Sic Power Module
Semiconductor Power Devices Having Gate Dielectric Layers with Improved Breakdown Characteristics and Methods of Forming Such Devices
Interface Layer Control Methods for Semiconductor Power Devices and Semiconductor Devices Formed Thereof
Trenched Power Device with Segmented Trench and Shielding
Semiconductor Device Having a First Barrier Layer Formed on a Gate Pad and Gate Electrode and an Isolation Layer Provided Between the First Barrier Layer and a Second Barrier Layer Formed Thereon
Application:
16/863,642 →
Publication:
US 2021/0343847
Conduction Enhancement Layers for Electrical Contact Regions in Power Devices
Integrated Circuit Having Die Attach Materials with Channels and Process of Implementing the Same
Group III-Nitride High-Electron Mobility Transistors Configured with Recessed Source and/or Drain Contacts for Reduced On State Resistance and Process for Implementing the Same
Application:
16/876,752 →
Publication:
US 2021/0359118
Contact Structures for Semiconductor Devices
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Semiconductor Power Devices Having Graded Lateral Doping in the Source Region
Power Devices with a Hybrid Gate Structure
Application:
16/907,163 →
Publication:
US 2021/0399128
Laser-Assisted Method for Parting Crystalline Material
Power Semiconductor Devices Having Multilayer Gate Dielectric Layers That Include an Etch Stop/Field Control Layer and Methods of Forming Such Devices
High Voltage Power Module
Power Module
Vertical Semiconductor Device with Improved Ruggedness
Shielding Arrangements for Transformer Structures
Application:
16/942,082 →
Publication:
US 2022/0037080
Methods and Apparatuses Related to Shaping Wafers Fabricated by Ion Implantation
Application:
16/950,414 →
Publication:
US 2021/0066081
Power Semiconductor Devices Having Gate Trenches and Buried Edge Terminations and Related Methods
Sidewall Dopant Shielding Methods and Approaches for Trenched Semiconductor Device Structures
Power Silicon Carbide Based Semiconductor Devices with Improved Short Circuit Capabilities and Methods of Making Such Devices
Trench Bottom Shielding Methods and Approaches for Trenched Semiconductor Device Structures
Edge Termination Structures for Semiconductor Devices
Power Module Having an Elevated Power Plane with an Integrated Signal Board and Process of Implementing the Same
Electronic Device Packages with Internal Moisture Barriers
Vertical Power Transistor Device
Patent:
49,913 →
Application:
17/080,062 →
Power Semiconductor Devices Including a Trenched Gate and Methods of Forming Such Devices
Field Effect Transistor with at Least Partially Recessed Field Plate
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
Semiconductor Die with Improved Ruggedness
Transistor Packages with Improved Die Attach
Packaged Transistor Having Die Attach Materials with Channels and Process of Implementing the Same
Protection Structures for Semiconductor Devices with Sensor Arrangements
Power Semiconductor Devices with Improved Overcoat Adhesion and/or Protection
Passivation Structures for Semiconductor Devices Having Patterned Structures Over Edge Termination Regions
Application:
17/088,686 →
Publication:
US 2022/0140132
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
Semiconductor Devices Including an Offset Metal to Polysilicon Gate Contact
Application:
17/096,147 →
Publication:
US 2022/0149165
Semiconductor Power Devices Having Multiple Gate Trenches and Methods of Forming Such Devices
Methods and Systems for Component Analysis, Sorting, and Sequencing Based on Component Parameters and Devices Utilizing the Methods and Systems
Finfet Power Semiconductor Devices
Power Transistor with Soft Recovery Body Diode
Semiconductor Devices for Improved Measurements and Related Methods
Large Dimension Silicon Carbide Single Crystalline Materials with Reduced Crystallographic Stress
Group III-Nitride High-Electron Mobility Transistors with Buried P-Type Layers and Process for Making the Same
Large Diameter Silicon Carbide Wafers
Process, System, and Device for Determining a Related Product
Application:
17/138,193 →
Publication:
US 2022/0207464
Radio Frequency Transistor Amplifiers Having Widened and/or Asymmetric Source/Drain Regions for Improved on-Resistance Performance
Devices Incorporating Stacked Bonds and Methods of Forming the Same
High Electron Mobility Transistors Having Improved Drain Current Drift and/or Leakage Current Performance
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Packaged Electronic Devices Having Dielectric Substrates with Thermally Conductive Adhesive Layers
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
Group Iii-Nitride High-Electron Mobility Transistors with Gate Connected Buried P-Type Layers and Process for Making the Same
Power Semiconductor Device with Reduced Strain
Integrated Power Module
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
Semiconductor Devices Having Gate Resistors with Low Variation in Resistance Values
Wide Bandgap Semiconductor Device with Sensor Element
Power Component Configured for Improving Partial Discharge Performance and System and Process of Implementing the Same
Power Transistor with Soft Recovery Body Diode
Carrier-Assisted Method for Parting Crystalline Material Along Laser Damage Region
Power Module Having Electrical Interconnections Using Mechanical Fittings and Process of Implementing the Same
Power Module
Circuits and Group Iii-Nitride Transistors with Buried P-Layers and Controlled Gate Voltages and Methods Thereof
Circuits and Group Iii-Nitride High-Electron Mobility Transistors with Buried P-Type Layers Improving Overload Recovery and Process for Implementing the Same
Group Iii-Nitride Transistors with Back Barrier Structures and Buried P-Type Layers and Methods Thereof
Field Effect Transistor with Selective Channel Layer Doping
Field Effect Transistors with Modified Access Regions
Field Effect Transistor with Selective Modified Access Regions
Field Effect Transistor with Source-Connected Field Plate
Multilayer Encapsulation for Humidity Robustness and Related Fabrication Methods
Device and Process for Fault Detection of a Power Device
Reduced Optical Absorption for Silicon Carbide Crystalline Materials
Package for Power Electronics
Power Semiconductor Die Having a Combination of Active Area and Termination Region Area Being Less Than 90% of Total Die Area
Application:
17/357,103 →
Publication:
US 2022/0416077
Superjunction Power Semiconductor Devices Formed via Ion Implantation Channeling Techniques and Related Methods
Semiconductor Devices Having Asymmetric Integrated Gate Resistors for Balanced Turn-on/Turn-Off Behavior
Power Semiconductor Devices Including Angled Gate Trenches
Encapsulation Stack for Improved Humidity Performance and Related Fabrication Methods
Interconnect Metal Openings Through Dielectric Films
Application:
17/390,316 →
Publication:
US 2023/0029763
Arrangements of Power Semiconductor Devices for Improved Thermal Performance
Semiconductor Device Incorporating a Substrate Recess
Vertical Power Devices Fabricated Using Implanted Methods
Contact and Die Attach Metallization for Silicon Carbide Based Devices and Related Methods of Sputtering Eutectic Alloys
Transistor Semiconductor Die with Increased Active Area
Transistor Device Structure with Angled Wire Bonds
Multiple Silicide Process for Separately Forming N-Type and P-Type Ohmic Contacts and Related Devices
Application:
17/505,744 →
Publication:
US 2023/0124215
Transistor with Ohmic Contacts
Compact Power Module
Packaged Semiconductor Devices, and Package Molds for Forming Packaged Semiconductor Devices
Edge Termination for Power Semiconductor Devices and Related Fabrication Methods
Group Iii-Nitride High-Electron Mobility Transistors with a Buried Metallic Conductive Material Layer and Process for Making the Same
Package for Power Electronics
Limiting Failures Caused by Dendrite Growth on Semiconductor Chips
Laser-Assisted Method for Parting Crystalline Material
Wide Bandgap Unipolar/Bipolar Transistor
Interface Layer Control Methods for Semiconductor Power Devices and Semiconductor Devices Formed Thereof
Multilayer Encapsulation for Humidity Robustness and Highly Accelerated Stress Tests and Related Fabrication Methods
Application:
17/591,704 →
Publication:
US 2022/0384290
Die Backside Metallization Methods and Apparatus
Application:
17/658,691 →
Publication:
US 2023/0326897
Semiconductor Die Including a Metal Stack
Application:
17/665,191 →
Publication:
US 2023/0253359
Power Semiconductor Devices Having Multilayer Gate Dielectric Layers That Include an Etch Stop/Field Control Layer and Methods of Forming Such Devices
Methods of Forming Semiconductor Power Devices Having Graded Lateral Doping
Radio Frequency Transistor Amplifiers Having Self-Aligned Double Implanted Source/Drain Regions for Improved on-Resistance Performance and Related Methods
Semiconductor Packages with Increased Power Handling
Methods for Dicing Semiconductor Wafers Having a Metallization Layer and Semiconductor Devices Made by the Methods
Systems and Processes for Increasing Semiconductor Device Reliability
Support Shield Structures for Trenched Semiconductor Devices
Power Semiconductor Device with Shallow Conduction Region
Application:
17/705,172 →
Publication:
US 2023/0327026
Packaged Electronic Devices Having Transient Liquid Phase Solder Joints and Methods of Forming Same
Power Semiconductor Devices Including Multiple Gate Bond Pads
Application:
17/712,649 →
Publication:
US 2023/0120729
Transistor Including a Discontinuous Barrier Layer
Dual Inline Power Module
Dynamic Performance of on-Chip Current Sensors
Application:
17/736,720 →
Publication:
US 2023/0361212
Group Iii Nitride-Based Monolithic Microwave Integrated Circuits Including Static Random Access Memory Blocks with Associated Addressing and Buffering Circuits
Vertical Power Devices Having Mesas and Etched Trenches Therebetween
Power Semiconductor Devices Having Moisture Barriers
Application:
17/747,128 →
Publication:
US 2023/0378010
Circuits and Methods for Controlling Bidirectional Cllc Converters
Trench Bottom Shielding Methods and Approaches for Trenched Semiconductor Device Structures
Field Effect Transistor with Multiple Stepped Field Plate
Power Package Having Connected Components and Processes Implementing the Same
Application:
17/837,640 →
Publication:
US 2023/0402360
Semiconductor Devices Having Asymmetric Integrated Lumped Gate Resistors for Balanced Turn-on/Turn-Off Behavior and/or Multiple Spaced-Apart Lumped Gate Resistors for Improved Power Handling
Application:
17/843,010 →
Publication:
US 2023/0023195
Power Module
Gate Trench Power Semiconductor Devices Having Trench Shielding Patterns Formed During the Well Implant and Related Methods
Application:
17/845,120 →
Publication:
US 2023/0411446
Semiconductor Devices Having on-Chip Gate Resistors
Gate Trench Power Semiconductor Devices Having Improved Breakdown Performance and Methods of Forming Such Devices
Application:
17/847,650 →
Publication:
US 2023/0420527
Methods and Systems for Implementing a Modular Platform Implementing Active Devices
Application:
17/848,526 →
Publication:
US 2023/0422399
Packages with Backside Mounted Die and Exposed Die Interconnects and Methods of Fabricating the Same
Methods of Forming Ohmic Contacts on Semiconductor Devices with Trench/Mesa Structures
Methods of Forming Uniformly Doped Deep Implanted Regions in Silicon Carbide and Silicon Carbide Layers Including Uniformly Doped Implanted Regions
Application:
17/849,037 →
Publication:
US 2023/0420575
Semiconductor Device with Selectively Grown Field Oxide Layer in Edge Termination Region
Semiconductor Device Packages with Exposed Heat Dissipating Surfaces and Methods of Fabricating the Same
Top Side Cooled Semiconductor Packages
Application:
17/849,316 →
Publication:
US 2023/0420329
Optimization of Power Module Performance via Parasitic Mutual Coupling
Gallium Nitride High-Electron Mobility Transistors with P-Type Layers and Process for Making the Same
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Multi-Cavity Package Having Single Metal Flange
Application:
17/867,801 →
Publication:
US 2022/0352141
Electronic Devices with Reduced Ohmic to Ohmic Dimensions
Application:
17/893,277 →
Publication:
US 2024/0072125
Vertical Semiconductor Device with Improved Ruggedness
High Reliability Semiconductor Devices and Methods of Fabricating the Same
Application:
17/935,509 →
Publication:
US 2023/0019230
Device and Process for Implementing Silicon Carbide (Sic) Surface Mount Devices
Application:
17/951,523 →
Publication:
US 2024/0105390
Transistor Package and Process of Implementing the Transistor Package
Application:
17/951,527 →
Publication:
US 2024/0105570
Barrier Structure for Dispersion Reduction in Transistor Devices
Application:
17/951,708 →
Publication:
US 2024/0105823
Silicon Carbide Device with Single Metallization Process for Ohmic and Schottky Contacts
Application:
17/957,737 →
Publication:
US 2024/0113235
Implanted Regions for Semiconductor Structures with Deep Buried Layers
Application:
17/961,032 →
Publication:
US 2024/0120202
Methods of Forming Semiconductor Structures and Resulting Semiconductor Structures
Application:
17/966,081 →
Publication:
US 2024/0128336
Semiconductor Devices with Additional Mesa Structures for Reduced Surface Roughness
Application:
17/977,003 →
Publication:
US 2024/0145537
Transistor Devices Including Self-Aligned Ohmic Contacts and Contact Regions and Related Fabrication Methods
Application:
18/063,787 →
Publication:
US 2024/0194751
Core-Shell Particle Die-Attach Material
Application:
18/074,079 →
Publication:
US 2024/0182757
Multiple Transport Level Tester System
Gate Trench Power Semiconductor Devices Having Self-Aligned Trench Shielding Regions and Related Methods
Application:
18/093,343 →
Publication:
US 2024/0234495
Device Design for Short-Circuit Protection of Transistors
Flip-Chip Field Effect Transistor Layouts and Structures
Application:
18/105,586 →
Publication:
US 2024/0266348
Power Semiconductor Devices Having Non-Rectangular Semiconductor Die for Enhanced Mechanical Robustness and Reduced Stress and Electric Field Concentrations
Application:
18/107,537 →
Publication:
US 2024/0274660
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
Metal Stack with Phonon Scattering Layer That Forms a Non-Ohmic Contact to a Semiconductor Layer
Application:
18/121,782 →
Publication:
US 2024/0313099
Semiconductor Devices with Integrated Test Structures
Application:
18/125,610 →
Publication:
US 2024/0321651
Semiconductor Devices with Integrated Test Areas
Application:
18/125,655 →
Publication:
US 2024/0321647
Power Semiconductor Devices Including a Trenched Gate and Methods of Forming Such Devices
Semiconductor Devices Having Gate Resistors with Low Variation in Resistance Values
Heteroepitaxial Semiconductor Devices with Enhanced Thermal Dissipation
Application:
18/137,797 →
Publication:
US 2024/0355918
Semiconductor Devices with Low Barrier Height Schottky Contacts
Application:
18/138,240 →
Publication:
US 2024/0355897
Power Electronics Package Layouts, Structures, and/or Configurations for One or More Power Devices and Processes Implementing the Same
Application:
18/145,502 →
Publication:
US 2024/0213124
Buried Shield Structures for Power Semiconductor Devices and Related Fabrication Methods
Application:
18/150,432 →
Publication:
US 2024/0234507
Semiconductor Device and Related Fabrication Method
Application:
18/152,130 →
Publication:
US 2024/0234370
Thermal Enhanced Power Semiconductor Package
Application:
18/154,353 →
Publication:
US 2024/0243031
Power Module Having an Elevated Power Plane with an Integrated Signal Board and Process of Implementing the Same
Power Semiconductor Devices Including Multiple Layer Metallization
Application:
18/160,765 →
Publication:
US 2024/0213196
Semiconductor Device Packages Including Multilayer Stacks with Improved Adhesion
Application:
18/161,144 →
Publication:
US 2024/0258217
Integrated Power Module
Edge Termination Structures for Semiconductor Devices
Semiconductor Device Having Semiconductor Structure with Polarity Inverting Layer
Application:
18/164,205 →
Publication:
US 2024/0266419
Semiconductor Structure for Improved Radio Frequency Thermal Management
Application:
18/164,249 →
Publication:
US 2024/0266426
Hourglass-Shaped Vias for Group Iii-Nitride Semiconductor Devices
Application:
18/168,985 →
Publication:
US 2024/0274507
Electroless Die-Attach Process for Semiconductor Packaging
Application:
18/169,492 →
Publication:
US 2024/0274514
Metal Nitride Core-Shell Particle Die-Attach Material
Nitrogen-Polar Group III-Nitride Semiconductor Device with Isolation Implant Regions
Application:
18/173,534 →
Publication:
US 2024/0290876
Electric Field Modification for Nitrogen-Polar Group III-Nitride Semiconductor Devices
Application:
18/175,231 →
Publication:
US 2024/0290847
Power Semiconductor Package
Application:
18/179,036 →
Publication:
US 2024/0304507
Field Reducing Structures for Nitrogen-Polar Group III-Nitride Semiconductor Devices
Die-Coat Material Configured to Enhance Device Reliability and Devices and Processes Implementing the Same
Application:
18/187,804 →
Publication:
US 2024/0321659
High-Performance Stress Buffer Die-Coat and Devices and Processes Implementing the Same
Application:
18/187,924 →
Publication:
US 2024/0321663
Silicon Carbide Device with Single Metallization Process for Ohmic and Schottky Contacts
Application:
18/211,429 →
Publication:
US 2024/0421192
Silicon Carbide Semiconductor Devices with Superjunctions
Application:
18/213,500 →
Publication:
US 2024/0429272
Electronic Device Packages with Internal Moisture Barriers
Silicon Carbide Thermal Bridge Integrated on a Low Thermal Conductivity Substrate and Processes Implementing the Same
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
Semiconductor Power Devices Having Multiple Gate Trenches and Methods of Forming Such Devices
Application:
18/302,843 →
Publication:
US 2023/0261073
Power Semiconductor Devices Including Beryllium Metallization
Application:
18/304,869 →
Publication:
US 2024/0355738
Signal Loop Busbars and Semiconductor Power Modules Including the Same and Processes of Implementing the Same
Application:
18/305,976 →
Publication:
US 2024/0356322
Method for Reducing Parasitic Capacitance and Increasing Peak Transconductance While Maintaining on-State Resistance and Related Devices
Field Peak Reduction in Semiconductor Devices with Metal Corner Rounding
Application:
18/330,013 →
Publication:
US 2024/0413218
Improved Thermal and Electrical Conductivity Between Metal Contacts Utilizing Spring Pin Connectors
Low Contact Resistance in Semiconductor Devices with Implanted Regions
Application:
18/333,632 →
Publication:
US 2024/0421193
Rf Amplifier Devices and Methods of Manufacturing Including Modularized Designs with Flip Chip Interconnections and Integration into Packaging
Application:
18/334,466 →
Publication:
US 2023/0327624
Semiconductor Package
Application:
18/336,358 →
Publication:
US 2024/0421029
Die-Attach Fillet Height Reduction
Application:
18/336,376 →
Publication:
US 2024/0421044
Power Module
Integrated Resistors with Increased Sheet Resistance for Rf Applications and Methods of Fabricating the Same
Application:
18/337,657 →
Publication:
US 2024/0429230
Low Reverse Leakage Current Power Schottky Diodes Having Reduced Current Crowding at the Lower Blocking Junction Corners
Application:
18/340,418 →
Publication:
US 2024/0429323
Implantation for Isolated Channel Structures in Group III-Nitride Semiconductor Devices
Application:
18/340,471 →
Publication:
US 2024/0429314
Topside Cooling for Semiconductor Device
Application:
18/340,503 →
Publication:
US 2024/0429120
Power Package Configured with Additional Functionality
Application:
18/346,561 →
Publication:
US 2025/0014973
Methods and Systems for Matching Both Dynamic and Static Parameters in Dies, Discretes, and/or Modules and Methods and Systems Based on the Same
Application:
18/347,980 →
Publication:
US 2023/0361089
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
Application:
18/355,683 →
Publication:
US 2023/0369486
Submounts with Stud Protrusions for Semiconductor Packages
Application:
18/358,616 →
Publication:
US 2025/0038055
Protection of Mesa Edges in Semiconductor Devices
Application:
18/370,995 →
Publication:
US 2025/0107169
Group Iii-Nitride High-Electron Mobility Transistors Configured with a Low Resistance Contact Layer for Source and/or Drain Contacts and Process for Implementing the Same
Application:
18/383,733 →
Publication:
US 2025/0142915
Carrier-Assisted Method for Parting Crystalline Material Along Laser Damage Region
Application:
18/394,999 →
Publication:
US 2024/0128085
Device Having a Rate of Current Change Limiter and Process of Implementing the Same
Monolithic Bidirectional Jfet Switch
Application:
18/399,226 →
Publication:
US 2025/0220982
Silicon Carbide Based Semiconductor Devices with Ring-Shaped Channel Regions and/or Channel Regions That Extend in Multiple Directions in Plan View
Application:
18/403,068 →
Publication:
US 2025/0220995
Power Semiconductor Devices Including Shape-Memory Metallization
Application:
18/405,721 →
Publication:
US 2025/0226338
Electroless Deposition Process for Semiconductor Devices
Application:
18/410,443 →
Publication:
US 2025/0201565
Laser-Assisted Method for Parting Crystalline Material
Power Semiconductor Device Having Improved Transient Handling Without Field Insulating Layer
Application:
18/412,190 →
Publication:
US 2025/0234619
Thermal Management Enhancement of Electronic Components
Application:
18/417,295 →
Publication:
US 2025/0240867
Gate Trench Power Semiconductor Devices Having Deep Trench Shield Connection Patterns
Application:
18/417,348 →
Publication:
US 2025/0241040
Submounts with Stud Protrusions for Semiconductor Packages
Application:
18/419,128 →
Publication:
US 2025/0038056
Anti-Reflective Layer for Protecting an N-Polar Group III-Nitride Semiconductor Structure
Application:
18/422,617 →
Publication:
US 2025/0246428
Thermally Stable FinFET Device for High Temperature Operation
Application:
18/422,677 →
Publication:
US 2025/0248064
Sic Vjfet with Edge Termination for Dual Tilted Gate Implants
Application:
18/427,184 →
Publication:
US 2025/0248079
Vertical Power Devices Fabricated Using Implanted Methods
Optimization of Power Module Performance via Parasitic Mutual Coupling
Compact Power Module
Power Semiconductor Devices Including Integrated Polysilicon Devices
Application:
18/430,542 →
Publication:
US 2025/0254909
Power Semiconductor Devices with Stacked Layers
Application:
18/430,866 →
Publication:
US 2025/0254943
Edge Termination Using Implant Damage
Application:
18/431,115 →
Publication:
US 2025/0254934
Devices Implementing Selective Cap Layers and Processes for Implementing the Same
Application:
18/438,015 →
Publication:
US 2025/0261394
Layered Metallization in Power Semiconductor Packages
Application:
18/443,031 →
Publication:
US 2025/0266350
Semiconductor Wafer with Process Control Monitor Structures
Application:
18/443,886 →
Publication:
US 2025/0266304
Wide Bandgap Trench Gate Semiconductor Device with Buried Gate
Application:
18/449,458 →
Publication:
US 2025/0063800
Power Semiconductor Devices Having Gate Trenches with Asymmetrically Rounded Upper and Lower Trench Corners and/or Recessed Gate Electrodes and Methods of Fabricating Such Devices
Application:
18/453,414 →
Publication:
US 2025/0072044
Thermal Enhanced Power Semiconductor Package
Application:
18/456,782 →
Publication:
US 2024/0243106
Wide Bandgap Transistors with Gate-Source Field Plates
Application:
18/464,599 →
Publication:
US 2023/0420526
Semiconductor Transistors Having Minimum Gate-to-Source Voltage Clamp Circuits
Application:
18/466,031 →
Publication:
US 2023/0418319
Power Semiconductor Device with Balancing Shunt Structure
Application:
18/466,487 →
Publication:
US 2025/0089316
Corrosion Resistant Metal Structures for Wide Bandgap Semiconductor Devices
Application:
18/471,003 →
Publication:
US 2025/0098199
Buried Shield Structures for Power Semiconductor Devices Including Segmented Support Shield Structures for Reduced on-Resistance and Related Fabrication Methods
Application:
18/472,343 →
Publication:
US 2024/0234567
Power Semiconductor Device Having Shaped Trench Ends
Application:
18/475,298 →
Publication:
US 2025/0107124
Semiconductor Die Bonding
Application:
18/475,370 →
Publication:
US 2025/0105196
Power Silicon Carbide Based Semiconductor Devices with Selective Jfet Implants That Are Self-Aligned with the Well Regions and Methods of Making Such Devices
Application:
18/476,452 →
Publication:
US 2025/0113531
Gate Trench Power Semiconductor Devices Having Deep Support Shields and Methods of Fabricating Such Device
Application:
18/482,097 →
Publication:
US 2025/0120133
Gate Trench Power Semiconductor Devices Having Shaped Deep Support Shields That Reduce Cell Pitch and on-State Resistance
Application:
18/482,105 →
Publication:
US 2025/0120119
Multifunctional Adhesion Promoter for Semiconductor Device Packages
Application:
18/487,665 →
Publication:
US 2025/0122413
Direct Bonded Semiconductor Die Package
Application:
18/488,284 →
Publication:
US 2025/0125231
Gate Trench Power Semiconductor Devices Having Trench Shielding Regions and Support Shields That Extend to Different Depths
Application:
18/493,838 →
Publication:
US 2025/0142877
Gate Trench Power Semiconductor Devices Having Channels with Horizontal and Vertical Segments
Application:
18/495,085 →
Publication:
US 2025/0142868
Power Modules Having Encapsulation Stress and Strain Mitigating Configurations
Application:
18/501,858 →
Publication:
US 2025/0149395
Power Electronics Package Having Signal Connections for Multiple Power Devices
Application:
18/502,911 →
Publication:
US 2025/0149506
Power Semiconductor Device with Reduced Strain
Packaged Transistor with Channeled Die Attach Materials and Process of Implementing the Same
Application:
18/505,197 →
Publication:
US 2024/0079320
Split Support Shield Structures for Trenched Semiconductor Devices with Integrated Schottky Diodes
Application:
18/508,322 →
Publication:
US 2025/0159948
Gate Trench Power Semiconductor Devices with Deep Jfet Patterns
Application:
18/510,734 →
Publication:
US 2025/0169128
Enhanced Isolation for on-Chip Current Sensors
Application:
18/510,756 →
Publication:
US 2025/0169166
Mask Integration for Trenched Semiconductor Device Structures
Application:
18/514,038 →
Publication:
US 2025/0169105
Reversible Power Module and a Process of Implementing a Reversible Power Module
Application:
18/518,105 →
Publication:
US 2025/0167081
Group Iii-Nitride High-Electron Mobility Transistors with Buried P-Type Layers and Process for Making the Same
Underfill for Large Area Attaches for Semiconductor Packages
Application:
18/524,126 →
Publication:
US 2025/0183119
Power Semiconductor Package
Application:
18/525,028 →
Publication:
US 2025/0183105
Multi-Gate Switch Field Effect Transistor
Application:
18/526,986 →
Publication:
US 2025/0185277
Package for Power Electronics
Substrates for Power Semiconductor Devices
Application:
18/537,427 →
Publication:
US 2025/0194190
Power Semiconductor Devices
Application:
18/537,435 →
Publication:
US 2025/0194191
Asymmetric Edge Termination
Application:
18/540,135 →
Publication:
US 2025/0203960
Engineered Interconnect Structures for Enhanced Bonding Strength
Application:
18/541,571 →
Publication:
US 2025/0201674
Group Iii-Nitride High-Electron Mobility Transistors Configured with a Low Resistance Contact Layer for Source and/or Drain Contacts and Process for Implementing the Same
Application:
18/545,517 →
Publication:
US 2025/0142918
Electroless Deposition Process for Semiconductor Devices
Application:
18/545,648 →
Publication:
US 2025/0201740
Silicon Carbide Power Devices Having Expanded Creepage Distances
Application:
18/581,339 →
Publication:
US 2025/0267893
Integrated Active Cooling in Power Packages
Application:
18/584,179 →
Publication:
US 2025/0273536
Device Package Having a Contactless Sensor and Process of Implementing the Same
Application:
18/586,142 →
Publication:
US 2025/0273528
Dc Link Snubber Device Configured for Connection to a Power Module and/or the Like and Processes of Implementing the Same
Application:
18/589,080 →
Publication:
US 2025/0274036
Two Component Chemical Mechanical Polishing
Grind Wheel Design for Low Edge-Roll Grinding
Additives for Grinding Semiconductor Workpieces
Application:
18/598,859 →
Publication:
US 2025/0285873
Mosfets with Implanted Charge Compensation Regions
Application:
18/598,866 →
Publication:
US 2024/0387620
Disc Grinding for Semiconductor Wafers on Polishing System
Application:
18/598,871 →
Publication:
US 2025/0282021
Vertical Jfet Semiconductor Devices with Avalanche Current Ballast Resistance
Application:
18/607,711 →
Publication:
US 2025/0293152
Semiconductor Devices Having Intrinsic Gate-to-Drain Capacitances That Are Only Partly in Series with a Gate Resistor
Application:
18/607,712 →
Publication:
US 2025/0294865
Gate Trench Power Semiconductor Devices Having Trench Shielding Regions and Methods of Forming the Same
Application:
18/610,394 →
Publication:
US 2025/0301699
Power Devices with Multiple Metal Layer Thicknesses
Application:
18/612,302 →
Publication:
US 2025/0300105
Power Devices with Barrier Metal Extension and Sealing
Application:
18/612,356 →
Publication:
US 2025/0300106
Cellular Wafer Structure
Application:
18/616,611 →
Publication:
US 2025/0311382
Power Module Implementing True and Partial Source Kelvin Interconnections for Enhancing Switching Performance and Process of Implementing the Same
Application:
18/618,823 →
Publication:
US 2025/0309113
Power Silicon Carbide Based Semiconductor Devices Having Super Junction Drift Regions and Methods of Forming Such Devices
Application:
18/623,114 →
Publication:
US 2025/0311318
Method of Uniform NiSi Deposition
Application:
18/627,134 →
Publication:
US 2025/0316486
Laser-Based Surface Processing for Semiconductor Workpiece
Fill-In Planarization System and Method
Patent:
12,362,237 →
Application:
18/628,231 →
Off Axis Laser-Based Surface Processing Operations for Semiconductor Wafers
Laser Edge Shaping for Semiconductor Wafers
Patent:
12,269,123 →
Application:
18/628,275 →
Gate Trench Power Semiconductor Devices Having Enhanced Avalanche Robustness and Methods of Forming Such Devices
Application:
18/633,618 →
Publication:
US 2025/0324680
Vertical Jfet Semiconductor Devices with Localized Avalanche Breakdown
Application:
18/633,687 →
Publication:
US 2025/0324679
Photoionization Detector
Application:
18/633,985 →
Publication:
US 2024/0345041
Power Transistor with Soft Recovery Body Diode
Application:
18/636,381 →
Publication:
US 2024/0266432
Method and System for Conditioning a Polishing Pad
Application:
18/643,511 →
Publication:
US 2025/0326085
Trench Gate Wide Bandgap Junction Field Effect Transistors with Termination Regions Having Planar Upper Surfaces
Application:
18/646,862 →
Publication:
US 2025/0338571
Gate Trench Power Semiconductor Devices Having Split Gate Electrodes
Application:
18/646,883 →
Publication:
US 2025/0338547
Methods and Systems for Component Analysis, Sorting, and Sequencing Based on Component Parameters and Devices Utilizing the Methods and Systems
Application:
18/649,479 →
Publication:
US 2024/0282645
Semiconductor Devices Having Metal Gate Runners with Asymmetric Outer Gate Runners, Unevenly-Spaced Inner Gate Runners and/or Spine-Rib Inner Gate Runners with Multiple Ribs
Application:
18/655,542 →
Publication:
US 2025/0343117
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
Integration of Liner in Passivation Stack
Application:
18/656,059 →
Publication:
US 2025/0343091
Edge Termination for Power Semiconductor Devices and Related Fabrication Methods
Application:
18/660,332 →
Publication:
US 2024/0290832
Laser-Based Processing for Semiconductor Wafers
Patent:
12,315,729 →
Application:
18/661,994 →
Electrical Discharge Machining Processing for Semiconductor Workpiece
Workpiece Surface Processing System for Semiconductor Wafers
Application:
18/663,862 →
Publication:
US 2025/0357182
Polishing Pad Assembly for Electrochemical Mechanical Polishing
Application:
18/663,883 →
Publication:
US 2025/0353136
Ionic Slurry for Electrochemical Mechanical Polishing
Application:
18/663,911 →
Publication:
US 2025/0357131
Multi-Scale Autoencoders for Semiconductor Workpiece Understanding
Patent:
12,322,087 →
Application:
18/674,427 →
Treatments for Improving Fracture Strength for Semiconductor Workpiece
Application:
18/680,764 →
Publication:
US 2025/0372382
Power Discrete Package Having Symmetric Pinouts and Process of Implementing the Same
Application:
18/733,442 →
Publication:
US 2025/0372520
Surface Processing of Semiconductor Workpieces
Method and System to Measure Optical Characteristics of Light-Transmissive Materials
Application:
18/737,609 →
Publication:
US 2025/0379107
Trench Based Semiconductor Devices with Heterojunction Gate
Application:
18/738,646 →
Publication:
US 2025/0380467
Nondestructive Characterization for Crystalline Wafers
Trench Based Semiconductor Devices with Increased Planarity
Application:
18/742,626 →
Publication:
US 2025/0386569
Reduced Optical Absorption for Silicon Carbide Crystalline Materials
Application:
18/751,832 →
Publication:
US 2024/0344239
Gate-Controlled Semiconductor Devices Having Temperature Compensated Gate Resistances
Application:
18/755,884 →
Publication:
US 2026/0006884
Fiducial Structure for Inspection of Semiconductor Workpieces
Application:
18/759,307 →
Publication:
US 2026/0002886
Multi-Channel Workpiece Inspection System
Application:
18/759,356 →
Publication:
US 2026/0002874
High Throughput High Dynamic Range (HDR) Microscopy
Application:
18/759,385 →
Publication:
US 2026/0004401
Large Diameter Silicon Carbide Wafers
Detecting Defects in Semiconductor Material
Application:
18/770,846 →
Publication:
US 2026/0016361
Semiconductor Devices with Drain-Source Avalanche Breakdown
Application:
18/772,731 →
Publication:
US 2026/0020295
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
Application:
18/775,934 →
Publication:
US 2024/0367348
Boules with Boule-Handling Carrier Processing Methods
Application:
18/778,375 →
Publication:
US 2026/0021609
High Speed, Efficient Sic Power Module
Application:
18/779,946 →
Publication:
US 2024/0380320
Gate Trench Power Semiconductor Devices Having Shallow Trench Shields and Deep Support Shields
Application:
18/780,825 →
Publication:
US 2026/0032951
Trench Based Semiconductor Devices with Conformal Salicide Thickness
Application:
18/781,526 →
Publication:
US 2026/0032984
Wide Bandgap Semiconductor Device with Sensor Element
Application:
18/782,116 →
Publication:
US 2024/0379667
Multilayer Printed Circuit Board with Filling Segment Structures
Application:
18/782,438 →
Publication:
US 2025/0040030
Gate Trench Power Semiconductor Devices Having Deep Channel Regions and Related Methods of Fabricating Same
Application:
18/788,395 →
Publication:
US 2026/0040613
Stabilizing GAN Training by Regulating Learning Rates in Semiconductor Workpiece Inspection Models
Application:
18/789,165 →
Publication:
US 2026/0038246
Solid-State Circuit Breaker Configured with at Least One Fail-Open Mechanism and Process of Implementing the Same
Application:
18/791,725 →
Publication:
US 2026/0039105
Power Semiconductor Devices Including Angled Gate Trenches
Application:
18/792,813 →
Publication:
US 2024/0395927
Power Module
Application:
18/793,141 →
Publication:
US 2024/0395677
Non-Continuous Pad Structure for Power Semiconductor Devices and Power Semiconductor Devices Including Non-Continuous Pad Structures
Application:
18/796,522 →
Publication:
US 2026/0047470
Shape Model Generation and Use for Semiconductor Workpiece
Application:
18/802,817 →
Publication:
US 2026/0050246
Power Semiconductor Devices and Methods of Forming the Same
Application:
18/804,575 →
Publication:
US 2026/0052738
Encapsulation Delamination Prevention Structures at Die Edge
Application:
18/806,895 →
Publication:
US 2026/0053057
Stress Relief Features for Localized Die Stress Relief
Application:
18/807,029 →
Publication:
US 2026/0052994
Trench Based Semiconductor Devices with Epitaxially Regrown Layers
Application:
18/810,026 →
Publication:
US 2026/0059812
Semiconductor Devices Having Inner Gate Runners with Non-Orthogonal Inner Segments
Application:
18/810,884 →
Publication:
US 2026/0059837
Sidewall Dopant Shielding Methods and Approaches for Trenched Semiconductor Device Structures
Application:
18/813,208 →
Publication:
US 2024/0413197
Power Semiconductor Device Package
Application:
18/816,797 →
Publication:
US 2026/0068693
Semiconductor Devices with Drain-Source Connection for Avalanche Breakdown
Application:
18/826,969 →
Publication:
US 2026/0075901
Large Dimension Silicon Carbide Single Crystalline Materials with Reduced Crystallographic Stress
Application:
18/828,024 →
Publication:
US 2025/0006491
Trenched Diode Having Enhanced Forward Voltage Drop to Reverse Leakage Current Tradeoff and Method of Forming Such Device
Application:
18/830,713 →
Publication:
US 2026/0075887
Power Semiconductor Devices Including Deep Shielding Regions
Application:
18/830,731 →
Publication:
US 2026/0075904
System to Reduce Induced Subsurface Damage in Separation of Semiconductor Workpieces
Application:
18/830,879 →
Publication:
US 2026/0070158
Power Semiconductor Device Package
Application:
18/882,003 →
Publication:
US 2026/0076252
Dual Inline Power Module
Application:
18/930,630 →
Publication:
US 2025/0056738
Hybrid Seed Structure for Crystal Growth System
Patent:
12,454,768 →
Application:
18/941,479 →
Metallizations for Semiconductor Power Devices
Application:
18/950,476 →
Publication:
US 2025/0081579
Bulk Silicon Carbide Crystal Growth System with 3D-Printed Parts
Application:
18/963,082 →
Publication:
US 2026/0062832
Shaped Solid Silicon Carbide Vapor Source Material Structure for use in a Sublimation System for Growing Crystalline Silicon Carbide
Application:
18/963,103 →
Publication:
US 2026/0062831
Silicon Carbide Vapor Source Material for use in a Sublimation System for Growing Crystalline Silicon Carbide
Application:
18/963,117 →
Publication:
US 2026/0062833
Compact Power Module
Application:
18/981,173 →
Publication:
US 2025/0112211
Packaged Electronic Devices Having Dielectric Substrates with Thermally Conductive Adhesive Layers
Application:
19/013,061 →
Publication:
US 2025/0149432
Gate Trench Power Semiconductor Devices Having Shallow Trench Shields and Deep Support Shields
Application:
19/014,347 →
Publication:
US 2026/0032973
Laser Edge Shaping for Semiconductor Wafers
Application:
19/170,701 →
Publication:
US 2025/0312869
Multi-Scale Autoencoders for Semiconductor Workpiece Understanding
Application:
19/202,654 →
Publication:
US 2025/0363621
Laser-Based Processing for Semiconductor Wafers
Application:
19/209,065 →
Publication:
US 2025/0349543
System to Reduce Induced Subsurface Damage in Separation of Semiconductor Workpieces
Application:
19/229,272 →
Publication:
US 2026/0070263
Method and System to Measure Optical Characteristics of Light-Transmissive Materials
Application:
19/230,629 →
Publication:
US 2025/0377262
Wafer-Level Bond-Line Control
Application:
19/248,969 →
Publication:
US 2025/0323130
Semiconductor Workpiece Inspection System
Application:
19/252,080 →
Publication:
US 2026/0002875
Fill-In Planarization System and Method
Application:
19/264,064 →
Publication:
US 2025/0336723
Nondestructive Characterization for Crystalline Wafers
Application:
19/272,061 →
Publication:
US 2025/0351495
Laser-Based Surface Processing for Semiconductor Workpiece
Application:
19/299,783 →
Publication:
US 2025/0367767
Power Module
Patent:
954,667 →
Application:
29/663,171 →
Power Module
Patent:
903,590 →
Application:
29/663,172 →
Power Module
Patent:
909,310 →
Application:
29/663,502 →
Power Module
Patent:
908,632 →
Application:
29/663,505 →
Housing for a Power Module Assembly
Patent:
954,668 →
Application:
29/676,416 →
Power Module Having Pin Fins
Patent:
942,403 →
Application:
29/710,592 →
Power Semiconductor Package
Patent:
937,231 →
Application:
29/730,568 →
Power Module
Patent:
969,740 →
Application:
29/757,360 →
Power Module
Patent:
1,073,632 →
Application:
29/780,368 →
Power Semiconductor Package
Patent:
969,762 →
Application:
29/811,014 →
Power Module Having Pin Fins
Patent:
985,517 →
Application:
29/821,330 →
Power Module
Patent:
1,036,395 →
Application:
29/855,192 →
Semiconductor Package
Patent:
1,056,862 →
Application:
29/866,001 →
Power Module Having Pin Fins
Patent:
1,041,429 →
Application:
29/873,303 →
Power Module
Patent:
1,081,603 →
Application:
29/949,395 →
Silicon Carbide Vapor Source Material for use in a Sublimation System for Growing Crystalline Silicon Carbide
Application:
63/689,291 →
Shaped Solid Silicon Carbide Vapor Source Material Structure for use in a Sublimation System for Growing Crystalline Silicon Carbide
Application:
63/689,294 →
Bulk Silicon Carbide Crystal Growth System with 3D-Printed Parts
Application:
63/689,298 →
Related Assignments
(10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 14, 2014
From: REESE, BRAD ALAN; VALLE-MAYORGA, JAVIER ANTONIO; ESCORCIA-CARRANZA, IVONNE; PHAN, KHOA MINH
To: ARKANSAS POWER ELECTRONICS INTERNATIONAL, INC.
Reel/Frame 032886/0432 →
Merger and Change of Name
Jul 17, 2015
From: ARKANSAS POWER ELECTRONICS INTERNATIONAL, INC.; CREE FAYETTEVILLE, INC.
To: CREE FAYETTEVILLE, INC.
Reel/Frame 036118/0978 →
Merger
Aug 13, 2021
From: CREE FAYETTEVILLE, INC.
To: CREE, INC.
Reel/Frame 057291/0406 →
Change of Name
Oct 22, 2021
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 057891/0880 →
Change of Name
Feb 14, 2022
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 059085/0667 →
Security Interest
Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
Release of Security Interest in Intellectual Property Collateral at Reel/Frame No. 64185/0755
Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
Notice of Grant of Security Interest in Intellectual Property
Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
Notice of Grant of Security Interest in Intellectual Property
Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
Notice of Grant of Security Interest in Intellectual Property
Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →