Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides
View Patent ↗An improved field effect transistor formed in the Group III nitride material system includes a two part structure in which a chemical vapor deposited passivation layer of silicon nitride encapsulates a previously sputtered-deposited layer of silicon nitride. The sputtered layer provides some of the benefits of passivation and the chemical vapor deposited layer provides an excellent environmental barrier.
1. In a field effect transistor formed in the Group III nitride material system, the improvement in passivation comprising: a two part structure in which a chemical vapor deposited passivation layer of silicon nitride encapsulates a previously sputtered-deposited layer of silicon nitride; said sputtered layer providing some of the benefits of passivation and said chemical vapor deposited layer providing an excellent environmental barrier.
2. A high electron mobility transistor (HEMT) comprising:
a Group III heterostructure;
a first passivation structure on said Group III nitride heterostructure for reducing parasitic capacitance and minimizing device trapping; and
a second passivation structure on said first passivation structure for encapsulating said heterostructure and providing an environmental barrier;
said first passivation structure comprising at least one sputtered layer of non-stoichiometric nitride selected from the group consisting of silicon nitride, aluminum nitride, oxynitrides of silicon and oxynitrides of aluminum, and at least one chemical vapor deposited layer of silicon nitride for positioning said passivation layers further from said Group III nitride layer without fully encapsulating said heterostructure; and
said second passivation structure comprising an environmental barrier of stoichiometric nitrides.
3. A HEMT according to claim 2 wherein said heterostructure comprises a layer of aluminum gallium nitride and a layer of gallium nitride.
4. A HEMT according to claim 3 further comprising a first spacer layer of Group III nitride between said aluminum gallium nitride layer and said gallium nitride layer.
5. A HEMT according to claim 4 wherein said first spacer layer comprises aluminum nitride.
6. A HEMT according to claim 2 further comprising a gate contact to said Group III nitride heterostructure.
7. A HEMT according to claim 6 further comprising a second Group III nitride spacer layer between said gate contact and said heterostructure.
8. A HEMT according to claim 7 wherein said second spacer layer comprises gallium nitride.
9. A HEMT according to claim 6 further comprising respective source and drain ohmic contacts to said Group III nitride heterostructure and defining a channel therebetween.
10. A HEMT according to claim 6 wherein said heterostructure comprises a layer of aluminum gallium nitride on a layer of gallium nitride with said gate contact and said ohmic contacts on said aluminum gallium nitride layer.
11. A HEMT according to claim 2 further comprising a field plate separated from said gate contact by portions of said passivation structure.
12. A HEMT according to claim 2 wherein said second passivation structure comprises a sputtered stoichiometric layer of silicon nitride and a chemical vapor deposited stoichiometric layer of silicon nitride.
13. A HEMT according to claim 12 further comprising a field plate separated from said gate contact by said sputtered stoichiometric layer of silicon nitride and covered by said chemical vapor deposited stoichiometric layer of silicon nitride.
14. A HEMT according to claim 12 wherein said stoichiometric layer in said second passivation structure is substantially hydrogen free.
15. A HEMT according to claim 2 wherein said first passivation structure is substantially hydrogen free.
16. A HEMT according to claim 2 wherein said first passivation structure has a refractive index of between about 1.85 and 2.00.
17. A HEMT according to claim 2 wherein:
said sputtered layer of non-stoichiometric silicon nitride in said first passivation structure is between about 100 and 2000 angstroms thick;
said chemical vapor deposited layer of silicon nitride in said the first passivation structure is between about 100 and 3000 angstroms thick; and
said second passivation structure is between about 3000 and 8000 angstroms thick.
18. An insulated gate field effect transistor comprising:
a Group III nitride heterostructure;
respective source and drain ohmic contacts on said heterostructure;
an insulating layer on said heterostructure between said source and drain ohmic contacts;
a gate contact to said insulating layer on said heterostructure; and
respective first and second passivation structures on said heterostructure and ad least portions of said gate contact;
said first passivation structure comprising at least one sputtered layer of non-stoichiometric nitride selected from the group consisting of silicon nitride, aluminum nitride, oxynitrides of silicon and oxynitrides of aluminum, and at least one chemical vapor deposited layer of silicon nitride for positioning said passivation layers further from said Group III nitride layer without fully encapsulating said heterostructure; and
said second passivation structure comprising an environmental barrier of stoichiometric nitrides.
19. A transistor according to claim 18 wherein said second passivation structure comprises two layers of stoichiometric silicon nitride.
20. A transistor according to claim 18 wherein said insulating layer underneath said gate contact is underneath said first passivation structure.
21. A transistor according to claim 20 wherein said gate contact separates portions of said first sputtered layer of non-stoichiometric silicon nitride from one another.
22. A transistor according to claim 18 wherein said insulating layer covers portions of said sputtered layer of non-stoichiometric nitride in said first passivation structure.
23. A transistor according to claim 18 wherein said Group III nitride heterostructure comprises a layer of aluminum gallium nitride on a layer of gallium nitride with said gate insulating layer on said layer of aluminum gallium nitride.
24. A transistor according to claim 23 further comprising a first spacer layer between said gate insulating layer and said aluminum gallium nitride layer.
25. A transistor according to claim 24 wherein said first spacer layer comprises gallium nitride.
26. A transistor according to claim 23 further comprising a second spacer layer between said aluminum gallium nitride layer and said gallium nitride layer.
27. A transistor according to claim 26 wherein said second spacer layer comprises aluminum nitride.
28. A transistor according to claim 18 wherein said second passivation structure is substantially hydrogen free.
29. A transistor according to claim 18 wherein said first passivation structure is substantially hydrogen free.
30. A transistor according to claim 18 wherein said first passivation structure has a refractive index of between about 1.85 and 1.95.
31. A transistor according to claim 18 wherein:
said sputtered layer of non-stoichiometric silicon nitride in said first passivation structure is between about 1000 and 2000 angstroms thick;
said chemical vapor deposited layer of silicon nitride in said first passivation structure is between about 1000 and 3000 angstroms thick; and
said second passivation structure is between about 3000 and 8000 angstroms thick.