Semiconductor power devices having multiple gate trenches and methods of forming such devices
A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.
1. A semiconductor device, comprising:
a semiconductor layer structure; and
a gate formed in a gate trench in the semiconductor layer structure,
wherein the gate trench comprises:
a bottom surface comprising a first portion extending between first and second corners at a first level, and a second portion at a second level, wherein the second level is below the first level relative to a top of the gate trench; and
first and second sidewalls that extend from the top of the gate trench to the first and second levels, respectively.
2. The semiconductor device of claim 1 , wherein the bottom surface of the gate trench further comprises a third portion at a third level.
3. The semiconductor device of claim 1 , wherein the first and second portions are substantially parallel.
4. The semiconductor device of claim 1 , wherein the first and second sidewalls linearly extend from the top of the gate trench to the first and second levels, respectively.
5. A semiconductor device, comprising:
a semiconductor layer structure; and
a gate formed in a gate trench in the semiconductor layer structure,
wherein the gate trench has a bottom surface comprising a first portion and first and second corners at a first level and a second portion at a second level, different from the first level, and first and second sidewalls that extend from a top of the gate trench to the first and second levels, respectively,
wherein the semiconductor layer structure comprises:
a drift region having a first conductivity type;
a well region having a second conductivity type on the drift region; and
a deep shielding pattern having the second conductivity type below at least a portion of the bottom surface of the gate trench.
6. The semiconductor device of claim 4 , wherein the first corner is between the first sidewall of the gate trench and the first portion of the bottom surface of the gate trench; and
the second corner is between the first portion of the bottom surface of the gate trench and the second portion of the bottom surface of the gate trench.
7. The semiconductor device of claim 6 , wherein a second radius of curvature of the second corner is greater than a first radius of curvature of the first corner.
8. The semiconductor device of claim 6 , wherein the deep shielding pattern is between the second corner and the drift region.
9. The semiconductor device of claim 5 , wherein the semiconductor layer structure comprises a substrate, the second level is closer to the substrate than the first level, and the first and second sidewalls linearly extend from the top of the gate trench to the first and second levels, respectively.
10. The semiconductor device of claim 9 , wherein the substrate comprises silicon carbide.
11. The semiconductor device of claim 5 , wherein the deep shielding pattern extends to contact at least a portion of the well region.
12. The semiconductor device of claim 5 , wherein the bottom surface of the gate trench further comprises a third portion at a third level,
wherein the third portion of the bottom surface of the gate trench is on an opposite side of the second portion of the gate trench from the first portion of the gate trench, and
wherein the first level and the third level are at approximately a same level.
13. The semiconductor device of claim 5 , wherein the first corner is free of contact with the deep shielding pattern.
14. A semiconductor device, comprising:
a substrate having a first conductivity type;
a drift region having the first conductivity type on the substrate;
a well region having a second conductivity type on the drift region; and
a gate trench that penetrates into the well region and the drift region,
wherein the gate trench has a non-linear bottom surface comprising a first portion at a first level and a recess that extends towards the substrate, and wherein a second corner between the first portion and the recess has a greater radius of curvature than a first corner between a sidewall of the gate trench and the first portion.
15. The semiconductor device of claim 14 , further comprising a deep shielding pattern having the second conductivity type below at least a portion of the non-linear bottom surface of the gate trench.
16. The semiconductor device of claim 15 , wherein the deep shielding pattern extends on the recess in the non-linear bottom surface of the gate trench.
17. The semiconductor device of claim 15 , wherein the deep shielding pattern extends to contact at least a portion of the well region.
18. The semiconductor device of claim 15 , wherein the first corner is free of contact with the deep shielding pattern.
19. The semiconductor device of claim 14 , wherein a second portion of the non-linear bottom surface of the gate trench is at a second level, different from the first level.
20. The semiconductor device of claim 19 , wherein the non-linear bottom surface of the gate trench further comprises a third portion at a third level, and
wherein the third portion of the non-linear bottom surface of the gate trench is on an opposite side of the second portion of the gate trench from the first portion of the gate trench.
21. The semiconductor device of claim 20 , wherein the first level and the third level are at approximately a same level.
22. The semiconductor device of claim 19 , wherein the second portion of the non-linear bottom surface of the gate trench is within the recess.
23. The semiconductor device of claim 14 , wherein the recess is within a central portion of the non-linear bottom surface of the gate trench, and
wherein portions of the non-linear bottom surface are on opposite sides of the recess.
24. A semiconductor device, comprising:
a substrate having a first conductivity type;
a drift region having the first conductivity type on the substrate;
a well region having a second conductivity type on the drift region;
a gate trench that penetrates into the well region and the drift region, wherein the gate trench has a bottom surface comprising a first portion and a second portion, wherein the second portion is closer to the substrate than the first portion; and
a deep shielding pattern having the second conductivity type on the bottom surface and at least one sidewall of the gate trench.
25. The semiconductor device of claim 24 , wherein the deep shielding pattern is on the second portion of the bottom surface of the gate trench.
26. The semiconductor device of claim 25 , wherein the deep shielding pattern extends to contact at least a portion of the well region.
27. The semiconductor device of claim 24 , wherein the bottom surface of the gate trench further comprises a third portion, and
wherein the third portion of the bottom surface of the gate trench is on an opposite side of the second portion of the gate trench from the first portion of the gate trench.
28. The semiconductor device of claim 24 , wherein the gate trench further comprises:
a first corner between a first sidewall of the gate trench and the first portion of the bottom surface of the gate trench; and
a second corner between the first portion of the bottom surface of the gate trench and a second sidewall of the gate trench, wherein the second sidewall extends between the first portion and the second portion of the bottom surface of the gate trench.
29. The semiconductor device of claim 28 , wherein a second radius of curvature of the second corner is greater than a first radius of curvature of the first corner.
30. The semiconductor device of claim 28 , wherein a ratio of a first depth of the first sidewall to a second depth of the second sidewall is between 1 and 10.
31. The semiconductor device of claim 28 , wherein the at least one sidewall is a third sidewall that extends from a top of the gate trench to the second portion.
32. The semiconductor device of claim 28 , wherein the first corner is free of the deep shielding pattern.
33. The semiconductor device of claim 28 , further comprising a deep shielding pattern having the second conductivity type,
wherein the deep shielding pattern is between the second corner of the gate trench and the drift region.
34. The semiconductor device of claim 33 , wherein at least a portion of the first corner of the gate trench directly contacts the drift region without the deep shielding pattern between the portion of the first corner and the drift region.