Semiconductor devices having varying electrode widths to provide non-uniform gate pitches and related methods
View Patent ↗Semiconductor devices including a plurality of unit cells connected in parallel are provided. Each of the unit cells have a first electrode, a second electrode and a gate finger. One of the first electrodes at a center of the semiconductor device has a first width and one of the first electrodes at a periphery of the semiconductor device has a second width, smaller than the first width. The second electrodes have a substantially constant width such that a pitch between the gate fingers is non-uniform. Related methods are also provided.
1. A semiconductor device comprising:
a plurality of unit cells connected in parallel, each of the unit cells having a first electrode, a second electrode and a gate finger, wherein at least one of the first electrodes at a center of the semiconductor device has a first width, at least one of the first electrodes at a periphery of the semiconductor device has a second width, smaller than the first width, and the second electrodes have a substantially constant width such that a pitch between the gate fingers is non-uniform.
2. The semiconductor device of claim 1 , wherein the non-uniform pitch between the gate fingers provides a substantially uniform junction temperature to a substantial majority of the gate fingers when in operation.
3. The semiconductor device of claim 1 , wherein the width of the second electrodes are narrower than the first and second widths and wherein a drain to source capacitance (C ds ) remains substantially constant in the plurality of unit cells when in operation.
4. The semiconductor device of claim 1 , wherein the plurality of unit cells comprise a plurality of unit cells arranged in a linear array.
5. The semiconductor device of claim 1 , wherein the pitch between the gate fingers is inversely related to a distance of the gate finger from the center of the semiconductor device.
6. The semiconductor device of claim 1 , wherein the pitch between the gate fingers at the periphery of the semiconductor device is less than a pitch between gate fingers at a center of the device.
7. The semiconductor device of claim 1 , wherein the plurality of unit cells comprise a plurality of metal semiconductor field effect transistor (MESFET) unit cells.
8. The semiconductor device of claim 1 , wherein the semiconductor device comprises a silicon carbide (SiC) metal semiconductor field effect transistor (MESFET), a gallium arsenide (GaAs) MESFET or a gallium Nitride (GaN) high electron mobility transistor (HEMT).
9. The semiconductor device of claim 1 , wherein the plurality of unit cells comprise a plurality of silicon carbide transistor unit cells or a plurality of gallium nitride transistor unit cells.
10. The semiconductor device of claim 1 , wherein the first and second widths may be from about 20 μm to about 60 μm.
11. The semiconductor device of claim 1 , wherein the non-uniform pitches between the gate fingers are from about 10 μm to about 90 μm.
12. The semiconductor device of claim 1 , wherein the first electrodes comprise source electrodes and the second electrodes comprise drain electrodes.
13. A field effect transistor (FET), comprising:
a plurality of unit cells connected in parallel, each of the unit cells having a source finger, a drain finger and a gate finger, wherein at least one of the source fingers at a center of the FET has a first width, at least one the source fingers at a periphery of the FET has a second width, smaller than the first width, and the drain fingers have a substantially constant width such that a pitch between the gate fingers is non-uniform, wherein the non-uniform pitch between the gate fingers provides a substantially uniform junction temperature to a substantial majority of the gate fingers when in operation.
14. The FET of claim 13 , wherein the width of the drain fingers is narrower than the first and second widths and wherein a drain to source capacitance (C ds ) remains substantially constant in the plurality of unit cells when in operation.
15. The FET of claim 13 , wherein the plurality of unit cells comprise a plurality of unit cells arranged in a linear array.
16. The FET of claim 13 , wherein the pitch between the gate fingers is inversely related to a distance of the gate finger from the center of the transistor.
17. The FET of claim 13 , wherein the pitch between the gate fingers at the periphery of the transistor is less than a pitch between gate fingers at a center of the device.
18. The FET of claim 13 , wherein the plurality of unit cells comprise a plurality of metal semiconductor field effect transistor (MESFET) unit cells.
19. The FET of claim 13 , wherein the metal semiconductor field effect transistor (MESFET) comprises a silicon carbide (SiC) MESFET, a gallium arsenide (GaAs) MESFET or a gallium Nitride (GaN) high electron mobility transistor (HEMT).
20. The FET of claim 13 , wherein the plurality of unit cells comprise a plurality of silicon carbide transistor unit cells or a plurality of gallium nitride transistor unit cells.
21. The FET of claim 13 , wherein the first and second widths may be from about 20 μm to about 60 μm.
22. The FET of claim 13 , wherein the non-uniform pitches between the gate fingers are from about 10 μm to about 90 μm.
23. A method of controlling a peak junction temperature in a semiconductor device having a plurality of gate fingers electrically connected in parallel, the method comprising varying widths of source fingers and keeping widths of drain fingers substantially constant such that a spacing between the gate fingers is non-uniform.
24. The method of claim 23 , wherein the spacing between the gate fingers in a central region of the device are spaced farther apart from adjacent gates than are gate fingers in a peripheral region of the device.
25. A method of forming a transistor comprising:
forming a plurality of unit cells connected in parallel, each of the unit cells having a source finger, a drain finger and a gate finger, wherein at least one of the source fingers at a center of the transistor has a first width, at least one of the source fingers at a periphery of the transistor has a second width, smaller than the first width, and the drain fingers have a substantially constant width such that a pitch between the gate fingers is non-uniform.
26. The method of claim 25 , wherein the non-uniform pitch between the gate fingers provides a substantially uniform junction temperature to a substantial majority of the gate fingers when in operation.
27. The method of claim 25 , wherein the width of the second electrodes are narrower than the first and second widths and wherein a drain to source capacitance (C ds ) remains substantially constant in the plurality of unit cells when in operation.
28. The method of claim 25 , wherein the plurality of unit cells comprise a plurality of unit cells arranged in a linear array.
29. The method of claim 25 , wherein the pitch between the gate fingers is inversely related to a distance of the gate finger from the center of the transistor.
30. The method of claim 25 , wherein the pitch between the gate fingers at the periphery of the transistor is less than a pitch between gate fingers at a center of the device.
31. The method of claim 25 , wherein the plurality of unit cells comprise a plurality of metal semiconductor field effect transistor (MESFET) unit cells.
32. The method of claim 25 , wherein the metal semiconductor field effect transistor (MESFET) comprises a silicon carbide (SiC) MESFET, a gallium arsenide (GaAs) MESFET or a gallium Nitride (GaN) high electron mobility transistor (HEMT).
33. The method of claim 25 , wherein the plurality of unit cells comprise a plurality of silicon carbide transistor unit cells or a plurality of gallium nitride transistor unit cells.
34. The method of claim 25 , wherein the first and second widths may be from about 20 μm to about 60 μm.
35. The method of claim 25 , wherein the non-uniform pitches between the gate fingers are from about 10 μm to about 90 μm.