Semiconductor device including a power transistor device and bypass diode
A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the source contact are separated from the drain contact by at least a drift layer. The Schottky bypass diode is coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed throughout the drift layer by the Schottky bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact within the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.
1. A semiconductor device comprising:
a substrate;
a drift layer on the substrate;
a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:
at least four junction implants in the drift layer opposite the substrate such that the at least four junction implants are separated from one another by a portion of the drift layer;
a gate oxide layer on the drift layer opposite the substrate such that the gate oxide layer at least partially overlaps each one of the at least four junction implants;
a gate contact on the gate oxide layer;
source contacts on the drift layer and above each of the at least four junction implants; and
a drain contact on the substrate; and
junction barrier Schottky bypass diodes comprising a Schottky contact separate from the source contacts on the drift layer opposite the substrate such that the Schottky contact only partially overlaps and runs between two of the at least four junction implants, and is laterally disposed between the source contacts.
2. The semiconductor device of claim 1 wherein a total area of each junction barrier Schottky bypass diode of the junction barrier Schottky bypass diodes is between 1.0 μm 2 and 10.0 μm 2 .
3. The semiconductor device of claim 1 wherein the substrate and the drift layer comprise silicon carbide.
4. A semiconductor device comprising:
a substrate;
a drift layer on the substrate;
a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:
at least four junction implants in the drift layer opposite the substrate such that the at least four junction implants are separated from one another by a portion of the drift layer;
a gate oxide layer on the drift layer opposite the substrate such that the gate oxide layer at least partially overlaps each one of the at least four junction implants;
a gate contact on the gate oxide layer;
source contacts on the drift layer and above each of the at least four junction implants; and
a drain contact on the substrate;
a first junction barrier Schottky bypass diode comprising a first Schottky contact separate from the source contacts on the drift layer opposite the substrate such that the first Schottky contact only partially overlaps and runs between two of the at least four junction implants, and is disposed between the source contacts; and
a second junction barrier Schottky bypass diode comprising a second Schottky contact separate from the source contacts on the drift layer opposite the substrate such that the second Schottky contact only partially overlaps and runs between two of the at least four junction implants, and is laterally disposed between the source contacts.
5. The semiconductor device of claim 4 wherein:
a doping concentration of the substrate is between about 1×10 18 cm −3 and 1×10 20 cm −3 ; and
a doping concentration of the drift layer is between about 3×10 14 cm −3 and 1.5×10 16 cm −3 .
6. The semiconductor device of claim 4 wherein the first Schottky contact and the second Schottky contact comprise a low barrier height Schottky metal.
7. The semiconductor device of claim 4 wherein a total area of the first junction barrier Schottky bypass diode and the second junction barrier Schottky bypass diode is between 1.0 μm 2 and 10.0 μm 2 .
8. The semiconductor device of claim 4 wherein the substrate and the drift layer comprise silicon carbide.
9. A method for manufacturing a semiconductor device comprising:
providing a substrate;
providing a drift layer on the substrate;
providing a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) by: implanting at least four junction implants in the drift layer opposite the substrate such that the at least four junction implants are separated from one another by a portion of the drift layer;
providing a gate oxide layer on the drift layer opposite the substrate such that the gate oxide layer at least partially overlaps each one of the at least four junction implants;
providing a gate contact on the gate oxide layer;
providing source contacts on the drift layer and above each of the at least four junction implants; and
providing a drain contact on the substrate; and
providing junction barrier Schottky bypass diodes by: providing Schottky contacts separate from the source contacts on the drift layer opposite the substrate such that each of the Schottky contacts only partially overlaps and runs between two of the at least four junction implants, and is laterally disposed between the source contacts; and
providing a cathode on the substrate opposite the drift layer, wherein the cathode is coupled to the drain contact.
10. The method of claim 9 wherein:
a doping concentration of the substrate is between about 1×10 18 cm −3 and 1×10 20 cm −3 ; and
a doping concentration of the drift layer is between about 3×10 14 cm −3 and 1.5×10 16 cm −3 .
11. The method of claim 9 wherein the Schottky contacts comprise a low-barrier height Schottky metal.