Normally-off semiconductor devices
View Patent ↗Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.
1. A transistor, comprising:
a Group III-nitride buffer layer;
a Group III-nitride barrier layer on the Group III-nitride buffer layer;
a non-conducting spacer layer on the Group III-nitride barrier layer, the Group III-nitride barrier layer and the spacer layer defining a trench extending through the barrier layer and exposing a portion of the buffer layer;
a gate structure on the spacer layer and in the trench; and
a gate electrode on the gate structure.
2. The transistor of claim 1 , wherein the trench is further defined by the buffer layer, the transistor further comprising:
a second non-conducting spacer layer on the gate electrode and the dielectric layer; and
a field plate on the second non-conducting spacer.
3. The transistor of claim 2 , wherein the field plate is electrically coupled to a source electrode or the gate electrode.
4. The transistor of claim 2 , wherein the second non-conducting spacer has a thickness of from about 500 Å to about 5000 Å.
5. The transistor of claim 1 , wherein the trench is further defined by the buffer layer, the transistor further comprising a thin GaN layer having a thickness of from about 2.0 to about 50.0 Å between the trench and the gate structure.
6. The transistor of claim 1 , wherein the gate structure comprises a dielectric layer and wherein the dielectric layer has a thickness of from about 60 Å to about 600 Å.
7. The transistor of claim 1 , wherein the trench is further defined by the buffer layer and wherein the gate structure comprises an aluminum nitride (AlN) layer on the spacer layer and in the trench and a dielectric layer on the AlN layer.
8. The transistor of claim 7 , wherein the AlN layer has a thickness of from about 1.0 Å to about 10.0 Å.
9. The transistor of claim 7 , wherein the AlN layer comprises an Aluminum Gallium Nitride (AlGaN) layer.
10. The transistor of claim 7 , further comprising a thin gallium nitride (GaN) layer having a thickness of from about 2.0 to about 50.0 Å between the AlN layer and the trench.
11. The transistor of claim 7 , wherein the gate structure further comprises a gallium nitride (GaN) layer on the AlN layer, the GaN layer being between the dielectric layer and the AlN layer.
12. The transistor of claim 11 , wherein the GaN layer has a thickness of from about 2.0 Å to about 30 Å.
13. The transistor of claim 11 , further comprising a thin gallium nitride (GaN) layer having a thickness of from about 2.0 to about 50.0 Å between the AlN layer and the trench.
14. The transistor of claim 1 , wherein the first non-conducting spacer comprises silicon nitride and has a thickness of from about 300 Å to about 3000 Å.
15. The transistor of claim 1 , wherein the gate electrode has a length of from about 0.5 μm to about 5.0 μm.
16. The transistor of claim 1 , wherein the transistor comprises a normally-off High Electron Mobility Transistor (HEMT).
17. A transistor, comprising:
a Group III-nitride barrier layer;
a non-conducting spacer layer on the Group III-nitride barrier layer, the spacer layer defining a trench extending through the spacer layer and exposing a portion of the barrier layer;
dielectric sidewall spacers that extend only on sidewalls of the non-conducting spacer layer in the trench;
a gate implant region in a portion of the barrier layer; and
a gate electrode in the trench on the implanted region and on the spacer layer.
18. The transistor of claim 17 , wherein the implant region has an implant dose of from about 5.0×10 12 cm −2 to about 1.0×10 14 cm −2 .
19. The transistor of claim 17 , wherein the dielectric sidewall spacers have a thickness of from about 1.0 nm to about 50.0 nm.
20. The transistor of claim 17 , further comprising:
a second non-conducting spacer layer on the gate electrode and the spacer layer; and
a field plate on the second non-conducting spacer.
21. The transistor of claim 20 , wherein the field plate is electrically coupled to a source electrode or the gate electrode.
22. The transistor of claim 20 , wherein the second non-conducting spacer has a thickness of from about 500 Å to about 5000 Å.
23. The transistor of claim 17 , wherein the trench extends into the barrier layer.
24. The transistor of claim 23 , wherein the trench extends from about 0 Å to about 200 Å into the barrier layer.
25. The transistor of claim 17 , wherein the transistor comprises a normally-off High Electron Mobility Transistor (HEMT).