Power module with improved reliability
A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.
1. A power module comprising:
a first terminal and a second terminal;
a plurality of silicon carbide (SiC) semiconductor die coupled between the first terminal and the second terminal, the plurality of semiconductor die configured so the power module:
provides a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation such that a resistance between the first terminal and the second terminal is less than 100 mΩ; and
provides a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking mode of operation such that a leakage current between the first terminal and the second terminal is less than 20 mA when a voltage of at least 80% of a rated voltage of the power module is provided across the first terminal and the second terminal, wherein the rated voltage of the power module is at least 600V and the power module is capable of maintaining the voltage of at least 80% of the rated voltage across the first terminal and the second terminal for a period of at least 1000 hours at a temperature of at least 85° C. and a relative humidity of at least 85% without failure.
2. The power module of claim 1 wherein each one of the plurality of semiconductor die comprises:
a substrate;
a drift layer over the substrate; and
a passivation layer stack over the drift layer, the passivation layer stack comprising at least four passivation layers such that a composition of the at least four passivation layers alternates between at least a first material and a second material.
3. The power module of claim 2 wherein the first material and the second material are different ones of silicon nitride (SiN), silicon-dioxide (SiO 2 ), and silicon-oxy-nitride (SiON).
4. The power module of claim 2 wherein the passivation layer stack has a thickness of at least 1.6 μm.
5. The power module of claim 2 wherein each one of the plurality of semiconductor die further comprises a back-side metallization layer on the substrate opposite the drift layer such that the back-side metallization layer is substantially free of silver.
6. The power module of claim 5 further comprising a power electronic substrate on which the plurality of semiconductor die are mounted via a die attach material, wherein the power electronic substrate and the die attach material are substantially free of silver.
7. The power module of claim 2 further comprising a power electronic substrate on which the plurality of semiconductor die are mounted via a die attach material, wherein the power electronic substrate and the die attach material are substantially free of silver.
8. The power module of claim 1 wherein each one of the plurality of semiconductor die comprises:
a substrate;
a drift layer over the substrate; and
a back-side metallization layer on the substrate opposite the drift layer, wherein the back-side metallization layer is substantially free of silver.
9. The power module of claim 8 wherein:
a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed in the drift layer of at least one of the plurality of semiconductor die; and
the back-side metallization layer provides a drain contact of the MOSFET.
10. The power module of claim 9 wherein:
a Schottky diode is formed in the drift layer of at least one of the plurality of semiconductor die; and
the back-side metallization layer provides an anode contact of the Schottky diode.
11. The power module of claim 8 wherein:
a Schottky diode is formed in the drift layer of at least one of the plurality of semiconductor die; and
the back-side metallization layer provides an anode contact of the Schottky diode.
12. The power module of claim 8 wherein the back-side metallization layer comprises tin, nickel, and gold.
13. The power module of claim 8 wherein each one of the plurality of semiconductor die further comprises a front-side metallization layer on the drift layer opposite the substrate, wherein the front-side metallization layer comprises a first layer of titanium and a second layer comprising aluminum, nickel, and gold over the first layer.
14. The power module of claim 1 further comprising a power electronic substrate, wherein the plurality of semiconductor die are mounted on the power electronic substrate.
15. The power module of claim 14 wherein the power electronic substrate is substantially free of silver.
16. The power module of claim 15 wherein the power electronic substrate is a direct bonded copper (DBC) power electronic substrate.
17. The power module of claim 15 wherein the plurality of semiconductor die are mounted on the power electronic substrate using a die attach material that is substantially free of silver.
18. The power module of claim 17 wherein the die attach material comprises tin and antimony.
19. The power module of claim 14 wherein the plurality of semiconductor die are mounted on the power electronic substrate using a die attach material that is substantially free of silver.
20. The power module of claim 19 wherein the die attach material comprises tin and antimony.
21. The power module of claim 19 further comprising a baseplate on which the power electronic substrate is mounted, wherein the power electronic substrate is mounted on the baseplate using a substrate attach material that is substantially free of silver.
22. The power module of claim 1 wherein:
the resistance between the first terminal and the second terminal during the forward conduction mode of operation is at least 0.1 mΩ; and
the leakage current between the first terminal and the second terminal during the forward blocking mode of operation is greater than 0.1 mA.
23. The power module of claim 1 wherein each one of the plurality of semiconductor die comprises:
a substrate;
a drift layer over the substrate; and
a passivation layer stack over the drift layer, the passivation layer stack comprising at least four passivation layers.
24. The power module of claim 23 wherein the passivation layer stack is at least 1.6 μm thick.
25. The power module of claim 1 wherein each one of the plurality of semiconductor die comprises:
a substrate;
a drift layer over the substrate; and
a passivation layer stack over the drift layer, the passivation layer stack comprising at least four alternating layers of silicon nitride (SiN), silicon-dioxide (SiO 2 ), and silicon-oxy-nitride (SiON).