Floating bond pad for power semiconductor devices
Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size.
1. A semiconductor die on which a semiconductor device is fabricated, comprising:
a substrate comprising an active area and a control contact area;
a first bond pad on at least a portion of the active area;
a floating control bond pad over the control contact area and laterally extending over a portion of the first bond pad, wherein a size of the floating control bond pad is at least a minimum size required for an electrical connection from the floating control bond pad to a package and the floating control bond pad results in at least a 50% decrease in wasted space which results in an increase in space for the active area under the floating control bond pad; and
a dielectric layer between the portion of the first bond pad and the floating control bond pad.
2. The semiconductor die of claim 1 wherein the dielectric layer is on the control contact area and laterally extends over at least the portion of the first bond pad such that the dielectric layer is between the control contact area and the floating control bond pad and between the portion of the first bond pad and the floating control bond pad, and the semiconductor die further comprises:
a conductive feature that electrically connects the floating control bond pad and the control contact area.
3. The semiconductor die of claim 1 wherein the semiconductor device is a power semiconductor device.
4. The semiconductor die of claim 3 wherein the power semiconductor device is one of a group consisting of: a power Metal Oxide Semiconductor Field Effect Transistor and a power Bipolar Junction Transistor.
5. The semiconductor die of claim 3 wherein the power semiconductor device is a vertical device, and the semiconductor die further comprises a third bond pad on a surface of the substrate opposite the first bond pad.
6. The semiconductor die of claim 1 wherein the semiconductor die is electrically coupled to the package via a plurality of bond pads comprising the first bond pad and the floating control bond pad.
7. The semiconductor die of claim 1 wherein the wasted space is under the floating control bond pad.
8. The semiconductor die of claim 1 wherein the floating control bond pad results in at least a 75% reduction in wasted space under the floating control bond pad.
9. A method of fabrication of a semiconductor device, comprising:
providing a substrate comprising an active area and a control contact area;
providing a first bond pad on at least a portion of the active area;
providing a dielectric layer on a first active area and directly on a second active area; and
providing a floating control bond pad over the control contact area and laterally extending over a portion of the first bond pad, wherein a size of the floating control bond pad is at least a minimum size required for an electrical connection from the floating control bond pad to a package and the floating control bond pad results in at least a 50% decrease in wasted space which results in an increase in space for the active area under the floating control bond pad.
10. The method of claim 9 wherein providing the floating control bond pad comprises:
providing the dielectric layer over the first bond pad and an exposed surface of the substrate;
etching the dielectric layer to expose at least some of the first bond pad; and
after etching the dielectric layer, providing the floating control bond pad on the dielectric layer such that the floating control bond pad is over the control contact area and laterally extends over the portion of the first bond pad.
11. The method of claim 10 wherein providing the dielectric layer comprises depositing the dielectric layer.
12. The method of claim 11 wherein depositing the dielectric layer comprises one of a group consisting of: depositing the dielectric layer via Chemical Vapor Deposition and sputtering the dielectric layer.
13. The method of claim 10 wherein providing the dielectric layer comprises spin-coating the dielectric layer.
14. The method of claim 9 wherein providing the floating control bond pad comprises:
providing the dielectric layer over the first bond pad and an exposed surface of the substrate;
providing the floating control bond pad on the dielectric layer such that the floating control bond pad is over the control contact area and laterally extends over the portion of the first bond pad; and
after providing the floating control bond pad, etching the dielectric layer to expose at least some of the first bond pad.
15. The method of claim 9 wherein the semiconductor device is a power semiconductor device.
16. The method of claim 15 wherein the power semiconductor device is one of a group consisting of a power Metal Oxide Semiconductor Field Effect Transistor and a power Bipolar Junction Transistor.
17. The method of claim 15 wherein the power semiconductor device is a vertical device, and the method further comprises providing a third bond pad on a surface of the substrate opposite the first bond pad.
18. The method of claim 9 further comprising electrically connecting the semiconductor device to the package via a plurality of bond pads comprising the first bond pad and the floating control bond pad.
19. The method of claim 9 wherein the wasted space is under the floating control bond pad.
20. The method of claim 9 wherein the floating control bond pad results in at least a 75% reduction in wasted space under the floating control bond pad.
21. A semiconductor die, comprising:
a substrate having an active area;
a first bond pad on a first area of the semiconductor die;
a dielectric layer on a portion of the first bond pad; and
a floating control bond pad on a second area of the semiconductor die and laterally extending over the dielectric layer on the portion of the first bond pad such that the floating control bond pad laterally extends over the portion of the first bond pad on the first area of the semiconductor die, wherein a size of the floating control bond pad is at least a minimum size required for an electrical connection from the floating control bond pad to a package and the floating control bond pad results in at least a 50% decrease in wasted space which results in an increase in space for the first area under the floating control bond pad.
22. The semiconductor die of claim 21 wherein the semiconductor die is electrically coupled with the package, and a first electrical connection is provided from the first bond pad to the package and a second electrical connection that is different from the first electrical connection is provided from the floating control bond pad to the package.