Contact structures for semiconductor devices
Contact structures for semiconductor devices are disclosed. Contact structures that include a metal layer and a substrate of a semiconductor device may be annealed to provide suitable contact resistance. Localized annealed regions may be formed in a pattern within the contact structure to provide a desired contact resistance while reducing exposure of other portions of the semiconductor device to anneal conditions. The annealed regions may be formed in patterns that reduce intersections between annealed regions and fracture planes of the substrate, thereby improving mechanical robustness of the semiconductor device. The patterns may include annealed regions formed in lines that are nonparallel with fracture planes of the substrate. The patterns may also include annealed regions formed in lines that are nonparallel with peripheral edges of the substrate.
1. A semiconductor device comprising:
a substrate comprising a crystal structure that forms a plurality of fracture planes; and
a contact on the substrate, the contact comprising a plurality of annealed regions that are arranged along a plurality of lines, each line of the plurality of lines being formed by annealed regions of the plurality of annealed regions that are sequential next-closest neighbors with one another, the plurality of lines being nonparallel with the plurality of fracture planes.
2. The semiconductor device of claim 1 , wherein the substrate comprises a silicon carbide (SiC) substrate.
3. The semiconductor device of claim 2 , wherein the fracture planes comprise {1 1 00} crystallographic planes of SiC.
4. The semiconductor device of claim 2 , where the SiC substrate comprises 4H SiC.
5. The semiconductor device of claim 2 , wherein the contact further comprises a metal layer on the SiC substrate, and the plurality of annealed regions form a silicide of the metal layer.
6. The semiconductor device of claim 5 , wherein the metal layer comprises nickel and the silicide comprises nickel silicide.
7. The semiconductor device of claim 1 , wherein each line of the plurality of lines comprises at least three annealed regions of the plurality of annealed regions.
8. The semiconductor device of claim 1 , wherein each line of the plurality of lines is nonparallel with any peripheral edge of the substrate.
9. The semiconductor device of claim 1 , wherein certain lines of the plurality of lines are parallel with other lines of the plurality of lines.
10. The semiconductor device of claim 1 , wherein certain lines of the plurality of lines are nonparallel with other lines of the plurality of lines.
11. The semiconductor device of claim 1 , wherein a spiral pattern is formed by an individual line of the plurality of lines or by the plurality of lines when each line of the plurality of lines is aligned in an end-to-end arrangement.
12. The semiconductor device of claim 1 , wherein annealed regions of an individual line of the plurality of lines are positioned offset from annealed regions of a next adjacent line of the plurality of lines to form a zig-zag pattern.
13. The semiconductor device of claim 1 , wherein the contact is a backside contact formed on a bottom of the substrate, and the semiconductor device further comprises an active semiconductor region on a top of the substrate and one or more topside contacts on the active semiconductor region.
14. The semiconductor device of claim 13 , wherein the backside contact, the substrate, the active semiconductor region, and the one or more topside contacts form a metal-oxide-semiconductor field-effect transistor (MOSFET).
15. The semiconductor device of claim 14 , wherein the MOSFET comprises a silicon carbide (SiC) MOSFET.
16. The semiconductor device of claim 15 , wherein the backside contact, the substrate, the active semiconductor region, and the one or more topside contacts form a Schottky barrier diode.
17. The semiconductor device of claim 16 , wherein the Schottky barrier diode comprises a SiC Schottky barrier diode.
18. A semiconductor device comprising:
a silicon carbide (SiC) substrate comprising a first side, a second side that opposes the first side, and a plurality of peripheral edges;
an active semiconductor region on the first side of the SiC substrate; and
a backside contact on second side of the SiC substrate, the backside contact comprising a plurality of metal silicide regions that are spaced apart along the second side of the substrate, the plurality of metal silicide regions arranged along a plurality of lines, each line of the plurality of lines being formed by metal silicide regions of the plurality of metal silicide regions that are sequential next-closest neighbors with one another, the plurality of lines being nonparallel with the plurality of peripheral edges of the substrate.
19. The semiconductor device of claim 18 , wherein the backside contact comprises nickel and the plurality of metal silicide regions comprises nickel silicide.
20. The semiconductor device of claim 18 , wherein center points of the plurality of metal silicide regions are spaced apart by a spacing in a range from 30 μm to 60 μm.
21. The semiconductor device of claim 18 , wherein each line of the plurality of lines comprises metal silicide regions that are laterally surrounded by one or more metal regions.
22. The semiconductor device of claim 18 , wherein each metal silicide region of the plurality of metal silicide regions comprises a lower concentration region of metal silicide that laterally surrounds a higher concentration region of metal silicide.
23. The semiconductor device of claim 22 , wherein the lower concentration regions of next-closest neighbors of the plurality of metal silicide regions at least partially overlap within the plurality of lines.
24. The semiconductor device of claim 18 , wherein each line of the plurality of lines comprises metal silicide regions that are laterally surrounded by one or more metal regions and metal silicide regions that at least partially overlap with other metal silicide regions.
25. The semiconductor device of claim 18 , wherein the semiconductor device comprises a SiC metal-oxide-semiconductor field-effect transistor (MOSFET).
26. The semiconductor device of claim 18 , wherein the semiconductor device comprises a SiC Schottky barrier diode.
27. The semiconductor device of claim 18 , wherein one or more of the plurality of metal silicide regions are laterally surrounded by a metal layer.
28. A semiconductor device comprising:
a substrate comprising a crystal structure that forms a plurality of fracture planes; and
a contact on the substrate, the contact comprising a plurality of annealed regions that are arranged such that lines formed by next-closest annealed regions of the plurality of annealed regions are parallel with less than a third of the plurality of fracture planes.
29. The semiconductor device of claim 28 , wherein the lines formed by the next-closest annealed regions of the plurality of annealed regions are parallel with less than twenty percent of the plurality of fracture planes.
30. The semiconductor device of claim 28 , wherein the lines formed by the next-closest annealed regions of the plurality of annealed regions are parallel with less than ten percent of the plurality of fracture planes.
31. The semiconductor device of claim 28 , wherein the lines formed by the next-closest annealed regions of the plurality of annealed regions are formed to at least partially extend between two different peripheral edges of the substrate.
32. The semiconductor device of claim 31 , wherein the lines are formed to entirely extend between the two different peripheral edges of the substrate.
33. The semiconductor device of claim 28 , wherein the substrate comprises a silicon carbide (SiC) substrate and the plurality of fracture planes comprise {1 1 00} crystallographic planes of SiC.
34. The semiconductor device of claim 33 , wherein the contact comprises a metal layer on the SiC substrate, and the plurality of annealed regions form a silicide of the metal layer.
35. The semiconductor device of claim 34 , wherein the metal layer comprises nickel and the silicide comprises nickel silicide.
36. The semiconductor device of claim 28 , wherein the lines formed by the next-closest annealed regions of the plurality of annealed regions are nonparallel with any peripheral edge of the substrate.