Gallium Nitride high-electron mobility transistors with p-type layers and process for making the same
A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.
1. A high-electron mobility transistor comprising:
a substrate layer;
a buffer layer arranged on the substrate layer;
a barrier layer arranged on the buffer layer;
a drain arranged on the barrier layer;
a gate arranged on the barrier layer;
a source arranged on the barrier layer;
the source and the drain being configured such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and
a p-type material layer arranged on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer,
wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and
wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
2. The high-electron mobility transistor of claim 1 , wherein the length of the p-type material layer is configured and structured to increase discharge efficiency and limit breakdown.
3. The high-electron mobility transistor of claim 1 , wherein the length of the p-type material layer is configured and structured to retard an electric field, to increase electron confinement, and decrease leakage.
4. The high-electron mobility transistor of claim 1 , further comprising:
a plurality of unit cells; and
the plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
5. The high-electron mobility transistor of claim 1 , further comprising:
a p-type material contact arranged on and electrically coupled to the p-type material layer; and
a nucleation layer arranged on the substrate layer and the buffer layer is arranged on the nucleation layer,
wherein the substrate layer comprises Gallium Nitride; and
wherein the length of the p-type material layer is configured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
6. The high-electron mobility transistor of claim 1 , further comprising:
a recess in at least the barrier layer;
the source comprises a p-type material contact arranged in the recess; and
the p-type material contact is arranged on and electrically coupled to the p-type material layer.
7. The high-electron mobility transistor of claim 1 , wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
8. The high-electron mobility transistor of claim 1 , further comprising:
a second buffer layer arranged on the buffer layer on a side of the buffer layer opposite of the substrate layer,
wherein the barrier layer is arranged on the second buffer layer on a side opposite of the buffer layer.
9. A process of making high-electron mobility transistor comprising:
providing a substrate layer;
arranging a buffer layer on the substrate layer;
arranging a barrier layer arranged on the buffer layer;
arranging a source on the barrier layer;
arranging a drain on the barrier layer;
arranging a gate on the barrier layer;
configuring the source and the drain such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and
arranging a p-type material layer on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer,
wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and
wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
10. The process of making high-electron mobility transistor of claim 9 , further comprising configuring and structuring the length of the p-type material layer to increase discharge efficiency and limit breakdown.
11. The process of making high-electron mobility transistor of claim 9 , further comprising configuring and structuring the length of the p-type material layer to retard an electric field, to increase electron confinement, and decrease leakage.
12. The process of making high-electron mobility transistor of claim 9 , further comprising providing a plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
13. The process of making high-electron mobility transistor of claim 9 , further comprising:
arranging p-type material contact on and electrically coupled to the p-type material layer; and
arranging a nucleation layer on the substrate layer and the buffer layer is arranged on the nucleation layer,
wherein the substrate layer comprises Gallium Nitride; and
wherein the length of the p-type material layer is configured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
14. The process of making high-electron mobility transistor of claim 9 , further comprising:
forming a recess in at least the barrier layer; and
forming a source that comprises a portion having a p-type material contact arranged in the recess and the portion having the p-type material contact arranged on and electrically coupled to the p-type material layer; and
arranging the p-type material contact on and electrically coupled to the p-type material layer.
15. The process of making high-electron mobility transistor of claim 9 , wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
16. The process of making high-electron mobility transistor of claim 9 , further comprising:
providing a second buffer layer formed on the buffer layer;
providing a protective layer formed on the barrier layer; and
providing a nucleation layer arranged on the substrate layer,
wherein the length of the p-type material layer is configured and structured parallel to the surface of the buffer layer to extend at least from the source past the gate and the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the buffer layer.
17. The process of making high-electron mobility transistor of claim 9 , further comprising:
forming a nucleation layer on the substrate layer and arranging the buffer layer on the nucleation layer,
wherein the substrate layer comprises Silicon Carbide.
18. The process of making high-electron mobility transistor of claim 9 , further comprising:
forming a protective layer;
arranging a gate in part on the barrier layer and in part on the protective layer; and
forming a field plate structure extending a distance away from an edge of the gate.
19. The high-electron mobility transistor of claim 1 , wherein the p-type material layer extends to a point within about 0 to about 0.3 μm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
20. The high-electron mobility transistor of claim 1 , wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
21. The high-electron mobility transistor of claim 1 , wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
22. The high-electron mobility transistor of claim 1 , wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
23. The high-electron mobility transistor of claim 1 , wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
24. The high-electron mobility transistor of claim 1 , wherein the p-type material layer extends 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
25. The high-electron mobility transistor of claim 5 , wherein the p-type material contact comprises at least one metal overlayer.
26. The process of making high-electron mobility transistor of claim 9 , wherein the p-type material layer extends to a point within about 0 to about 0.3 μm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
27. The process of making high-electron mobility transistor of claim 9 , wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
28. The process of making high-electron mobility transistor of claim 9 , wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
29. The process of making high-electron mobility transistor of claim 9 , wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
30. The process of making high-electron mobility transistor of claim 9 , wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
31. The process of making high-electron mobility transistor of claim 9 , wherein the p-type material layer extends 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
32. The process of making high-electron mobility transistor of claim 13 , wherein the p-type material contact comprises at least one metal overlayer.