TRENCH BASED SEMICONDUCTOR DEVICES WITH INCREASED PLANARITY
A semiconductor device includes a semiconductor layer having an active region and a gate contact region adjacent the active region, a plurality of alternating mesa stripes and trenches in the active region, a gate contact pad on the semiconductor layer, and an under-gate mesa in the gate contact region beneath the gate contact pad. The semiconductor device may have a saw street at an outer periphery of the semiconductor layer, wherein a top surface of the saw street is at a same height above the substrate as top surfaces of the plurality of mesa stripes.
1 . A semiconductor device, comprising:
a semiconductor layer having an active region and a gate contact region adjacent the active region;
a plurality of alternating mesa stripes and trenches in the active region;
a gate contact pad on the semiconductor layer; and
an under-gate mesa in the gate contact region beneath the gate contact pad.
2 . The semiconductor device of claim 1 , further comprising an insulating layer between the under-gate mesa and the gate contact pad.
3 . The semiconductor device of claim 1 , wherein the under-gate mesa is electrically isolated from the plurality of alternating mesa stripes in the active region.
4 . The semiconductor device of claim 1 , wherein the under-gate mesa comprises an extension of one of the plurality of alternating mesa stripes in the active region.
5 . The semiconductor device of claim 4 , wherein the under-gate mesa has a width in the gate contact region that is greater than a width of mesa stripes in the active region.
6 . The semiconductor device of claim 1 , wherein at least one of the mesa stripes of the plurality of alternating mesa stripes in the active region extends into the gate contact region and beneath the gate contact pad.
7 . The semiconductor device of claim 1 , wherein the under-gate mesa has a width that is less than a width of mesa stripes in the active region.
8 . The semiconductor device of claim 1 , wherein a doping concentration in the under-gate mesa is lower than a doping concentration of mesa stripes in the active region.
9 . The semiconductor device of claim 1 , wherein the semiconductor device further comprises a plurality of alternating under-gate mesas and first trenches in the gate contact region beneath the gate contact pad, wherein the first trenches have a width that is less than a width of the plurality of trenches in the active region.
10 . The semiconductor device of claim 1 , further comprising:
a substrate, wherein the semiconductor layer is on the substrate; and
a saw street at an outer periphery of the semiconductor device, wherein a top surface of the saw street is at a same height above the substrate as top surfaces of the plurality of mesa stripes.
11 . A semiconductor device, comprising:
a semiconductor layer having an active region and a gate contact region adjacent the active region;
a plurality of alternating mesa stripes and trenches in the active region; and
a gate contact pad on the semiconductor layer;
wherein at least one mesa stripe of the plurality of mesa stripes extends beneath the gate contact pad.
12 . The semiconductor device of claim 11 , further comprising an insulating layer between the gate contact pad and a portion of the at least one mesa stripe that extends beneath the gate contact pad.
13 . The semiconductor device of claim 11 , wherein a portion of the at least one mesa stripe that extends beneath the gate contact pad has a width beneath the gate contact pad that is greater than a width of mesa stripes in the active region.
14 . The semiconductor device of claim 11 , wherein a portion of the at least one mesa stripe that extends beneath the gate contact pad has a width that is less than a width of mesa stripes in the active region.
15 . A semiconductor device, comprising:
a substrate;
a semiconductor layer on the substrate, the semiconductor layer having an active region and an edge termination region surrounding the active region;
a plurality of alternating mesa stripes and trenches in the active region;
a gate contact pad on the semiconductor layer within a gate contact region; and
a saw street at an outer periphery of the semiconductor layer, wherein a top surface of the saw street is at a same height above the substrate as top surfaces of the plurality of mesa stripes.
16 . The semiconductor device of claim 15 , wherein the semiconductor device comprises a junction field effect transistor, and wherein the saw streets at the outer periphery of the semiconductor layer are at drain potential of the semiconductor device.
17 . The semiconductor device of claim 15 , further comprising:
an under-gate mesa in the gate contact region beneath the gate contact pad.
18 . The semiconductor device of claim 17 , further comprising an insulating layer between the under-gate mesa and the gate contact pad.
19 . The semiconductor device of claim 17 , wherein the under-gate mesa is electrically isolated from the plurality of alternating mesa stripes in the active region.
20 . The semiconductor device of claim 17 , wherein the under-gate mesa comprises an extension of one of the plurality of alternating mesa stripes in the active region.
21 . The semiconductor device of claim 20 , wherein the under-gate mesa has a width in the gate contact region that is greater than a width of mesa stripes in the active region.
22 . The semiconductor device of claim 17 , wherein at least one of the mesa stripes of the plurality of alternating mesa stripes in the active region extends into the gate contact region and beneath the gate contact pad.
23 . The semiconductor device of claim 17 , wherein the under-gate mesa has a width that is less than a width of mesa stripes in the active region.