Power semiconductor devices including a trenched gate and methods of forming such devices
Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.
1. A semiconductor device comprising:
a semiconductor layer structure comprising a trench in an upper surface thereof, wherein the trench comprises a rounded upper corner and a rounded lower corner;
a dielectric layer in a lower portion of the trench, wherein a center portion of a top surface of the dielectric layer is curved, and the dielectric layer is on opposed sidewalls of the trench; and
a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure,
wherein the dielectric layer comprises:
a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench, the bottom dielectric layer comprising a rounded lower corner; and
a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.
2. The semiconductor device of claim 1 ,
wherein the center portion of the top surface of the dielectric layer that is curved is a center portion of a top surface of the gate dielectric layer.
3. The semiconductor device of claim 2 , wherein a center portion of a lower surface of the gate dielectric layer is curved.
4. The semiconductor device of claim 1 , wherein the bottom dielectric layer comprises an additive comprising boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and/or lead (Pb).
5. The semiconductor device of claim 1 , further comprising a barrier layer between the bottom dielectric layer and the gate dielectric layer.
6. The semiconductor device of claim 5 , wherein the semiconductor layer structure comprises a drift layer having a first conductivity type, a well having a second conductivity type in an upper portion of the drift layer and a source region having the first conductivity type in an upper portion of the well, and wherein an uppermost end of the barrier layer is closer to the bottom surface of the trench than a bottom surface of the well.
7. The semiconductor device of claim 5 , wherein the barrier layer comprises a silicon nitride layer and/or a silicon oxide layer.
8. The semiconductor device of claim 1 , wherein the bottom dielectric layer is a reflowed dielectric layer.
9. The semiconductor device of claim 1 , wherein the bottom dielectric layer comprises a spin-on-glass material.
10. The semiconductor device of claim 1 , wherein the semiconductor layer structure comprises 4H-silicon carbide, and a top surface of the semiconductor layer structure comprises the (0001) face of the 4H-silicon carbide.
11. The semiconductor device of claim 1 , wherein a center portion of a bottom surface of the trench is curved.
12. The semiconductor device of claim 1 , wherein an opening of the trench has a first width, and a bottom surface of the trench has a second width that is narrower than the first width.
13. A semiconductor device comprising:
a semiconductor layer structure comprising a trench in an upper surface thereof, wherein the trench comprises a rounded upper corner and a rounded lower corner;
a dielectric layer in a lower portion of the trench, wherein a center portion of a top surface of the dielectric layer is curved, and the dielectric layer is on opposed sidewalls of the trench; and
a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure),
wherein each of the rounded upper corner and the rounded lower corner has a radius of curvature in a range of 0.01 microns to 0.5 microns.
14. The semiconductor device of claim 13 , wherein the dielectric layer comprises:
a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench; and
a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.
15. A semiconductor device comprising:
a semiconductor layer structure comprising a trench in an upper surface thereof, wherein the trench comprises a rounded upper corner and a rounded lower corner;
a bottom dielectric layer in a lower portion of the trench;
a gate dielectric layer on a sidewall of the trench and on the bottom dielectric layer; and
a gate electrode in the trench and on the gate dielectric layer opposite the semiconductor layer structure,
wherein the bottom dielectric layer comprises a first concentration of an additive, and the gate dielectric layer has a second concentration of the additive that is lower than the first concentration.
16. The semiconductor device of claim 15 , wherein the additive comprises boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and/or lead (Pb).
17. The semiconductor device of claim 15 , further comprising a barrier layer between the bottom dielectric layer and the gate dielectric layer.
18. The semiconductor device of claim 17 , wherein the barrier layer comprises a silicon nitride layer and/or a silicon oxide layer.
19. A semiconductor device comprising:
a semiconductor layer structure comprising a trench in an upper surface thereof, wherein the trench comprises a rounded upper corner and a rounded lower corner;
a bottom dielectric layer in a lower portion of the trench;
a gate dielectric layer on a sidewall of the trench and on the bottom dielectric layer, the gate dielectric layer comprising a material different from the bottom dielectric layer; and
a gate electrode in the trench and on the gate dielectric layer opposite the semiconductor layer structure,
wherein the bottom dielectric layer comprises an additive, and the additive comprises boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and/or lead (Pb).
20. The semiconductor device of claim 19 , wherein the bottom dielectric layer comprises a first concentration of the additive, and the gate dielectric layer has a second concentration of the additive that is lower than the first concentration.
21. A semiconductor device comprising:
a semiconductor layer structure comprising a trench in an upper surface thereof, wherein the trench comprises a rounded lower corner;
a dielectric layer in a lower portion of the trench, wherein a center portion of a top surface of the dielectric layer is curved; and
a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure,
wherein the semiconductor layer structure comprises a drift layer having a first conductivity type, a well having a second conductivity type in an upper portion of the drift layer and a source region having the first conductivity type in an upper portion of the well, and
wherein the dielectric layer comprises:
a bottom dielectric layer on a bottom surface of the trench and on lower portions of sidewalls of the trench, the bottom dielectric layer comprising a rounded lower corner; and
a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.
22. The semiconductor device of claim 21 , wherein the lower portion of the trench is in the drift layer.
23. The semiconductor device of claim 22 , wherein the bottom dielectric layer comprises an additive comprising boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and/or lead (Pb).
24. The semiconductor device of claim 21 ,
wherein the center portion of the top surface of the dielectric layer that is curved is a center portion of a top surface of the gate dielectric layer.