Over-mold packaging for wide band-gap semiconductor devices
View Patent ↗A transistor package includes a lead frame and a gallium nitride (GaN) transistor attached to the lead frame. The lead frame and the GaN transistor are surrounded by an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa. Using an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa allows the over-mold to handle the heat produced by the GaN transistor while preventing damage to the GaN transistor due to thermal expansion and/or contraction of the over-mold.
1. A transistor package comprising:
a lead frame;
a wide band-gap semiconductor device attached to the lead frame using a die attach material with a bulk thermal conductivity greater than about 40 W/m-K and less than about 200 W/m-K and a flexural modulus less than about 20 GPa, and
an over-mold that is molded at least part way around the lead frame and that substantially surrounds the wide band-gap semiconductor device, the over-mold having a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa,
wherein the over-mold has a thermal coefficient of expansion less than about 50 ppm/° C. at temperatures above the glass transition temperature and a coefficient of thermal expansion less than 18 ppm/° C. at temperatures below the glass transition temperature.
2. The transistor package of claim 1 wherein the over-mold has a moisture absorption rate less than about 0.5%.
3. The transistor package of claim 1 wherein the over-mold has a glass transition temperature less than about 400° C.
4. The transistor package of claim 1 wherein the lead frame and the wide band-gap semiconductor device are substantially surrounded by the over-mold.
5. The transistor package of claim 1 wherein the wide band-gap semiconductor device is a gallium nitride (GaN) transistor.
6. The transistor package of claim 5 wherein the wide band-gap semiconductor device has a peak output power greater than about 150 W.
7. The transistor package of claim 6 wherein the wide band-gap semiconductor device has a peak output power greater than about 150 W when operated at a frequencies above 2.2 GHz and up to about 3.8 GHz.
8. The transistor package of claim 6 wherein the wide band-gap semiconductor device has a peak output power less than about 1 kW.
9. The transistor package of claim 1 wherein the wide band-gap semiconductor device is a gallium nitride (GaN) on silicon carbide (SiC) transistor.
10. A transistor package comprising:
a lead frame having a central region and first and second arms extending laterally from the central region;
a wide band-gap semiconductor device attached to the central region of the lead frame using a die attach material with a bulk thermal conductivity greater than about 40 W/m-K and less than about 200 W/m-K and a flexural modulus less than about 6 GPa;
an over-mold that is molded over a top surface of the lead frame and underneath the first and second arms of the lead frame, the over-mold substantially surrounding the wide band-gap semiconductor device, the over-mold having a glass transition temperature greater than about 135° C. and a thermal coefficient of expansion less than about 50 ppm/° C. at temperatures above the glass transition temperature and a thermal coefficient of expansion less than about 18 ppm/° C. at temperatures below the glass transition temperature; and
a first input/output pin that overlies the first arm and a second input/output pin that overlies the second arm,
wherein the over-mold extends between the lead frame and the first input/output pin and between the lead frame and the second input/output pin,
wherein a bottom surface of the lead frame that is opposite the wide band-gap semiconductor device is exposed through the over-mold, and
wherein the wide band-gap semiconductor device has an area of less than 16 mm 2 .
11. The transistor package of claim 10 wherein the over-mold has a glass transition temperature less than about 400° C.
12. The transistor package of claim 10 wherein the over-mold has a moisture absorption rate less than about 0.5%.
13. The transistor package of claim 10 wherein the lead frame and the wide band-gap semiconductor device are substantially surrounded by the over-mold.
14. The transistor package of claim 10 wherein the wide band-gap semiconductor device is a gallium nitride (GaN) transistor.
15. The transistor package of claim 10 wherein the wide band-gap semiconductor device has a peak output power greater than about 150 W.
16. The transistor package of claim 15 wherein the wide band-gap semiconductor device has a peak output power greater than about 150 W when operated at a frequency up to about 3.8 GHz.
17. The transistor package of claim 16 wherein the wide band-gap semiconductor device has a peak output power less than about 1 kW.
18. The transistor package of claim 10 wherein the wide band-gap semiconductor device is a gallium nitride (GaN) on silicon carbide (SiC) transistor.
19. The transistor package of claim 1 wherein a bottom surface of the lead frame that is opposite the wide band-gap semiconductor device is exposed through the over-mold.
20. The transistor package of claim 1 wherein the transistor package is an integrated circuit formed on a single integrated circuit chip that includes a wide band-gap transistor and at least one bandwidth limiting matching network.
21. The transistor package of claim 20 wherein the bandwidth limiting matching network is coupled between a radio frequency input and a gate of the wide band-gap transistor.
22. The transistor package of claim 20 wherein the bandwidth limiting matching network is coupled between a radio frequency output and a drain of the wide band-gap transistor.
23. The transistor package of claim 20 wherein the wide band-gap transistor comprises a first wide band-gap transistor, the transistor package further comprising a second wide band-gap transistor, and wherein the first and second wide band-gap transistors are arranged in a Doherty configuration.
24. The transistor package of claim 19 wherein the lead frame has a central region and first and second arms extending laterally from the central region.
25. The transistor package of claim 24 wherein the over-mold is molded over a top surface of the lead frame and underneath the first and second arms of the lead frame.
26. The transistor package of claim 25 further comprising a first input/output pin that overlies the first arm and a second input/output pin that overlies the second arm.
27. The transistor package of claim 26 wherein the over-mold extends between the lead frame and the first input/output pin and between the lead frame and the second input/output pin.