Transistors with a gate insulation layer having a channel depleting interfacial charge
View Patent ↗A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.
1. A metal-insulator-semiconductor field-effect transistor (MISFET) comprising:
a silicon carbide SiC layer having source and drain regions of a first conductivity type spaced apart therein, the SiC layer comprising a carbon (C)-face, a buried channel region containing first conductivity type impurity atoms extends between the spaced apart source and drain regions in the SiC layer;
a silicon dioxide layer directly on the C-face of the SiC layer between the source and drain regions, the silicon dioxide layer having a distinct interface along the C-face of the SiC layer that generates a fixed net charge that is the same polarity as majority carriers of the source region and depletes majority charge carriers from an adjacent portion of the buried channel region, wherein a product of a concentration of the first conductivity type impurity atoms in a per unit area and thickness of the buried channel region is equal to or less than an amount of fixed net charge per unit area provided by the silicon dioxide layer; and
a gate contact on the silicon dioxide layer over the buried channel region of the SiC layer between the source and drain regions.
2. The MISFET of claim 1 , wherein the net charge of the silicon dioxide layer depletes the majority charge carriers from the adjacent portion of the channel region when a voltage potential between the gate contact and the source region is zero.
3. The MISFET of claim 1 , wherein a region along the interface between the silicon dioxide layer and the SiC layer that provides the fixed net charge has a thickness no greater than 50 Å.
4. The MISFET of claim 1 , further comprising a gate insulation layer between the gate contact and the silicon dioxide layer.
5. The MISFET of claim 4 , wherein the gate insulation layer comprises silicon nitride.
6. The MISFET of claim 4 , wherein the gate insulation layer comprises silicon oxynitride.
7. The MISFET of claim 1 , wherein:
the channel region is an n-type region and the source and drain regions are n+ regions; and
the silicon dioxide layer has a net negative charge that depletes negative carriers from an adjacent portion of the buried channel region.
8. The MISFET of claim 7 , wherein:
the buried channel region has a n-type dopant concentration of from about 1×10 16 cm −3 to about 1×10 18 cm −3 and a thickness from about 0.1 μm to about 0.5×10 −5 μm; and
the source and drain regions each have a n-type dopant concentration from about 1×10 19 cm −3 to about 1×10 21 cm −3 .
9. The MISFET of claim 1 , wherein:
the silicon dioxide layer forms the distinct interface along the C-face of the SiC layer that generates a fixed net charge per unit area that is at least as high as a net charge generated by the first conductivity type impurity atoms in an adjacent unit area of the buried channel region when a voltage potential between the gate contact and the source region is zero.
10. The MISFET of claim 1 , wherein:
the carbon (C)-face of the SiC layer, on which the silicon dioxide layer is directly on, is substantially free of silicon atoms.