Granted Patent B2

US 10,192,980 · App. 15/424,209 · Granted Jan 29, 2019

Abstract

Claims (111)

1. A high-electron mobility transistor comprising:

a substrate layer;

a buffer layer arranged on the substrate layer;

a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided; and

a p+ type material layer being arranged on the p-type material layer,

wherein the p-type material layer is provided in one of the following locations: the substrate layer or a first layer arranged on the substrate layer;

wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer; and

wherein a thickness of the p-type material layer is greater than a thickness of the p+ type material layer.

2. The transistor of claim 1 ,

wherein the p+ type material layer comprises a length parallel to the surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer,

wherein the p-type material layer and the p+ type material layer are provided in one of the following locations: the substrate layer or the first layer arranged on the substrate layer,

wherein the substrate layer comprises SiC, and

wherein the buffer layer comprises at least one of the following: GaN, AlGaN, or AlN.

3. The transistor of claim 2 ,

wherein the p+ type material layer length parallel to the surface of the substrate layer extends at least from a source to at least to an edge of a gate adjacent to a drain; and

wherein the length of the p-type material layer is less than an entire length of the substrate layer.

4. The transistor of claim 1 ,

wherein the length of the p-type material layer is less than an entire length of the substrate layer parallel to the surface of the substrate layer.

5. The transistor of claim 4 ,

wherein the p-type material layer length parallel to a surface of the substrate layer extends at least from a source toward an edge of a gate adjacent a drain; and

wherein the length of the p-type material layer is greater than a length of the p+ type material layer.

6. A high-electron mobility transistor comprising:

a substrate layer;

a buffer layer arranged on the substrate layer;

a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided; and

a p+ type material layer being arranged on the p-type material layer,

wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer;

wherein the p-type material layer is provided in the substrate layer;

wherein the p-type material layer comprises aluminum implanted in the substrate layer; and

wherein a thickness of the p-type material layer is greater than a thickness of the p+ type material layer.

7. A high-electron mobility transistor comprising:

a substrate layer;

a buffer layer arranged on the substrate layer;

a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided; and

a p+ type material layer being arranged on the p-type material layer,

wherein the p-type material layer is provided in one of the following locations: the substrate layer or a first layer arranged on the substrate layer; and

wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer;

wherein the p+ type material layer comprises a length parallel to the surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer;

wherein the p+ type material layer is provided in the substrate layer;

wherein the p+ type material layer comprises aluminum implanted in the substrate layer; and

wherein a thickness of the p-type material layer is greater than a thickness of the p+ type material layer.

8. The transistor of claim 1 ,

wherein the p-type material layer is provided in the first layer arranged on the substrate layer;

wherein the first layer is SiC and comprises an epitaxial layer;

wherein the p-type material layer comprises aluminum in the epitaxial layer; and

wherein the p+ type material layer comprises a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer.

9. The transistor of claim 6 ,

wherein the p-type material layer is provided in the substrate layer;

wherein the p-type material layer is configured to have a depth greater than 0.5 μm;

wherein the p+ type material layer comprises a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer;

wherein the substrate layer comprises SiC; and

wherein the buffer layer comprises at least one of the following: GaN, AlGaN, or AlN.

10. The transistor of claim 7 ,

wherein the p-type material layer extends over the entire length of one of the following: the substrate layer and the first layer arranged on the substrate layer;

wherein the p+ type material layer comprises a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer;

wherein the substrate layer comprises SiC; and

wherein the buffer layer comprises at least one of the following: GaN, AlGaN, or AlN.

11. A method of making a high-electron mobility transistor comprising:

providing a substrate layer;

providing a buffer layer on the substrate layer;

providing a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided;

providing a p+ type material layer on the p-type material layer; and

providing the p-type material layer in one of the following locations: the substrate layer or a first layer arranged on the substrate layer,

wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer,

wherein a thickness of the p-type material layer is greater than a thickness of the p+ type material layer.

12. The method of claim 11 , further comprising:

providing the p+ type material layer further comprises providing the p+ type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided such that the length of the p+ type material layer is less than an entire length of the substrate layer parallel to the surface of the substrate layer;

providing the p-type material layer and the p+ type material layer in one of the following locations: the substrate layer or the first layer arranged on the substrate layer; and

the providing the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer further comprises implanting the p-type material layer utilizing channeling conditions.

13. The method of claim 12 ,

wherein the p+ type material layer length parallel to the surface of the substrate layer extends at least from a source to at least to an edge of a gate adjacent to the drain.

14. A method of making a high-electron mobility transistor comprising:

providing a substrate layer;

providing a buffer layer on the substrate layer;

providing a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided; and

providing a p+ type material layer on the p-type material layer,

wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer;

wherein the p-type material layer is provided in the substrate layer;

wherein the p-type material layer comprises aluminum implanted in the substrate layer;

wherein the p+ type material layer is provided in the substrate layer;

wherein the p+ type material layer comprises aluminum implanted in the substrate layer; and

wherein a thickness of the p-type material layer is greater than a thickness of the p+ type material layer.

15. The method of claim 14 ,

wherein the length of the p-type material layer is less than an entire length of the substrate layer parallel to the surface of the substrate layer;

wherein the substrate layer comprises SiC; and

wherein the buffer layer comprises at least one of the following: GaN, AlGaN, or AlN.

16. The method of claim 15 ,

wherein the p-type material layer length parallel to a surface of the substrate layer extends at least from a source toward an edge of a gate adjacent the drain; and

wherein the length of the p-type material layer parallel to a surface of the substrate layer is greater than a length of the p+ type material layer.

17. The method of claim 12 ,

wherein the p-type material layer is provided in the substrate layer;

wherein the p-type material layer is configured to have a depth greater than 0.5 μm; and

wherein the length of the p-type material layer is greater than a length of the p+ type material layer.

18. A high-electron mobility transistor comprising:

a substrate layer;

a buffer layer arranged on the substrate layer;

a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided; and

a p+ type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer, and the p+ type material layer being arranged in the p-type material layer,

wherein the p-type material layer and the p+ type material layer are provided in one of the following locations: the substrate layer or a first layer arranged on the substrate layer;

wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer;

wherein the length of the p-type material layer is less than an entire length of the substrate layer; and

wherein the p-type material layer is configured to have a depth greater than a depth of the p+ type material layer.

19. The transistor of claim 18 ,

wherein the p+ type material length parallel to the surface of the substrate layer extends at least from a source to at least to an edge of a gate adjacent to drain; and

wherein the length of the p-type material layer is greater than a length of the p+ type material layer.

20. The transistor of claim 18 ,

wherein the p-type material layer is provided in the substrate layer;

wherein the p-type material comprises aluminum implanted in the substrate layer;

wherein the p+ type material layer is provided in the substrate layer;

wherein the p+ type material layer comprises aluminum implanted in the substrate layer; and

wherein the length of the p-type material layer is greater than a length of the p+ type material layer.

Assignments (9)