Transistor including a discontinuous barrier layer
A transistor includes a first passivation layer on a semiconductor layer of the transistor between a source contact and a drain contact. The first passivation layer includes a portion having a topological change. The transistor further includes a discontinuous barrier layer on the portion of the first passivation layer having the topological change. The discontinuous barrier layer is configured to reduce ingress of moisture in the portion of the first passivation layer.
1. A transistor comprising:
a first passivation layer on a semiconductor layer of the transistor between a source contact and a drain contact, the first passivation layer comprising a portion having a topological change; and
a discontinuous barrier layer on the portion of the first passivation layer having the topological change, wherein the discontinuous barrier layer is configured to reduce ingress of moisture in the portion of the first passivation layer.
2. The transistor of claim 1 , further comprising:
a gate contact between the source contact and the drain contact; and
a field plate on a portion of the gate contact adjacent to the drain contact, wherein the portion of the first passivation layer having the topological change is on the field plate and the discontinuous barrier layer is on the portion of the first passivation layer.
3. The transistor of claim 1 , wherein the discontinuous barrier layer has a thickness that is in a range between about 25 nm to about 600 nm.
4. The transistor of claim 2 , wherein the field plate has a thickness that is thicker than a thickness of the discontinuous barrier layer.
5. The transistor of claim 3 , wherein the thickness of the field plate is greater than about 600 nm and the thickness of the discontinuous barrier layer is in a range between about 25 nm to less than about 600 nm.
6. The transistor of claim 2 , wherein the discontinuous barrier layer is a metal layer formed by a single metal comprising one of aluminum, gold, silver, silicon, titanium, and tantalum and the gate contact, the source contact, and the field plate, respectively, comprises a plurality of metals.
7. The transistor of claim 6 , wherein the plurality of metals does not include aluminum.
8. The transistor of claim 4 , wherein the discontinuous barrier layer does not contact to an electrical ground.
9. The transistor of claim 1 , further comprising:
a second passivation layer on the first passivation layer; and
wherein the discontinuous barrier layer is between the first passivation layer and the second passivation layer.
10. The transistor of claim 1 , wherein the discontinuous barrier layer extends over an entirety of the portion having the topological change.
11. The transistor of claim 1 , wherein the discontinuous barrier layer partially extends over the portion having the topological change.
12. The transistor of claim 1 , wherein the discontinuous barrier layer at least partially extends over the portion having the topological change adjacent the source contact.
13. The transistor of claim 1 , wherein the discontinuous barrier layer extends at least partially over the portion having the topological change adjacent the drain contact.
14. The transistor of claim 2 , wherein a length of the discontinuous barrier layer has a first end that extends from about a first edge of the gate contact and a second end that is closer to the first edge of the gate contact than to the drain contact.
15. The transistor of claim 2 , wherein a length of the discontinuous barrier layer has a first end that that extends from a portion of the gate contact and a second end that is closer to a first edge of the gate contact than to the drain contact.
16. The transistor of claim 2 , wherein a length of the discontinuous barrier layer has a first end the covers the gate contact and a second end that is closer to a first edge of the gate contact than to the drain contact.
17. The transistor of claim 2 , wherein a length of the discontinuous barrier layer has a first end that extends from about a first edge of the gate contact and a second end that is closer to the drain contact than to the first edge of the gate contact.
18. The transistor of claim 2 , wherein a length of the discontinuous barrier layer has a first end that that extends from a portion of the gate contact and a second end that is closer to the drain contact than to a first edge of the gate contact.
19. The transistor of claim 2 , wherein a length of the discontinuous barrier layer has a first end the covers the gate contact and a second end that is closer to the drain contact than to a first edge of the gate contact.
20. The transistor of claim 1 , further comprising:
a plurality of additional passivation layers having a respective portion of topological change on the first passivation layer; and
a plurality of additional discontinuous barrier layers, wherein the plurality of additional discontinuous passivation layers are positioned according to at least one of the following (i) between the first passivation layer and the second passivation layer, and (ii) respective ones of the additional discontinuous barrier layers are positioned between respective portions of topological change of the additional passivation layers.
21. The transistor of claim 1 , wherein the transistor comprises a high electron mobility transistor, HEMT.
22. A transistor comprising:
a first passivation layer on a semiconductor layer of the transistor between a source contact and a drain contact, the first passivation layer comprising a first portion having a topological change;
a first discontinuous barrier layer on the first portion of the first passivation layer having the topological change;
a second passivation layer on the first passivation layer on the semiconductor layer of the transistor between the source contact and the drain contact, the second passivation layer comprising a second portion having a topological change; and
a second discontinuous barrier layer on the second portion of the second passivation layer having the topological change, wherein the first and the second discontinuous barrier layers are configured to reduce ingress of moisture in the portions of the first and second passivation layers.
23. The transistor of claim 22 , further comprising:
a gate contact between the source contact and the drain contact; and
a field plate on a portion of the gate contact adjacent to the drain contact, wherein the portion of the first passivation layer having the topological change is on the field plate and the first discontinuous barrier layer is on the portion of the first passivation layer, and the second discontinuous barrier layer is on the portion of the second passivation layer.
24. The transistor of claim 22 , wherein the first and the second discontinuous barrier layers, respectively, have a thickness that is in a range between about 25 nm to about 600 nm.
25. The transistor of claim 23 , wherein the field plate has a thickness that is thicker than a thickness of the first and the second discontinuous barrier layers.
26. The transistor of claim 25 , wherein the thickness of the field plate is greater than about 600 nm and the thickness of the first and the second discontinuous barrier layers, respectively, is in a range between about 25 nm to less than about 600 nm.
27. The transistor of claim 23 , wherein the first and the second discontinuous barrier layers, respectively, is a metal layer formed by a single metal comprising one of aluminum, gold, silver, silicon, titanium, and tantalum and the gate contact, the source contact, and the field plate, respectively, comprises a plurality of metals.
28. The transistor of claim 27 , wherein the plurality of metals does not include aluminum.
29. The transistor of claim 23 , wherein the first and the second discontinuous barrier layers, respectively, do not contact to an electrical ground.
30. The transistor of claim 22 , further comprising:
a third passivation layer on the second passivation layer; and
wherein the first discontinuous barrier layer is between the first passivation layer and the second passivation layer, and the second discontinuous barrier layer is between the second passivation layer and the third passivation layer.
31. The transistor of claim 22 , wherein at least one of the first and the second discontinuous barrier layers, respectively, extends over an entirety of the respective first portion and/or second portion having the topological change.
32. The transistor of claim 22 , wherein at least one of the first and the second discontinuous barrier layers, respectively, partially extends over the respective first portion and/or second portion having the topological change.
33. The transistor of claim 22 , wherein at least one of the first and the second discontinuous barrier layers, respectively, at least partially extends over the respective first portion and/or second portion having the topological change adjacent the source contact.
34. The transistor of claim 22 , wherein at least one of the first and the second discontinuous barrier layers, respectively, extends at least partially over the respective first portion and/or second portion having the topological change adjacent the drain contact.
35. The transistor of claim 23 , wherein the second discontinuous barrier layer has a first end that extends from about a first edge of the gate contact and a second end that covers at least a portion of the gate contact and/or the field plate.
36. The transistor of claim 23 , wherein a length of the first discontinuous barrier layer has a first end that extends from about a first edge of the gate contact and a second end that is closer to the first edge of the gate contact than to the drain contact.
37. The transistor of claim 23 , wherein a length of the first discontinuous barrier layer has a first end that that extends from a portion of the gate contact and a second end that is closer to a first edge of the gate contact than to the drain contact.
38. The transistor of claim 23 , wherein a length of the first discontinuous barrier layer has a first end the covers the gate contact and a second end that is closer to a first edge of the gate contact than to the drain contact.
39. The transistor of claim 23 , wherein a length of the first discontinuous barrier layer has a first end that extends from about a first edge of the gate contact and a second end that is closer to the drain contact than to the first edge of the gate contact.
40. The transistor of claim 23 , wherein a length of the first discontinuous barrier layer has a first end that that extends from a portion of the gate contact and a second end that is closer to the drain contact than to a first edge of the gate contact.
41. The transistor of claim 23 , wherein a length of the first discontinuous barrier layer has a first end the covers the gate contact and a second end that is closer to the drain contact than to a first edge of the gate contact.
42. The transistor of claim 22 , further comprising:
a plurality of additional passivation layers having a respective portion of topological change on one of the first passivation layer and the second passivation layer; and
a plurality of additional discontinuous barrier layers, wherein the plurality of additional discontinuous passivation layers are positioned according to at least one of the following (i) between the first passivation layer and the second passivation layer, and (ii) respective ones of the additional discontinuous barrier layers are positioned between respective portions of topological change of the additional passivation layers.
43. The transistor of claim 21 , wherein the transistor comprises a high electron mobility transistor, HEMT.