High temperature performance capable gallium nitride transistor
View Patent ↗A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.
1. A transistor device, comprising:
a plurality of semiconductor layers;
a barrier layer on said semiconductor layers;
a spacer layer on at least a portion of said barrier layer; and
a gate electrode comprising a contact portion and a protective layer, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4 eV and an RF output power degradation of not more than 0.5 dB after 100 hours of operation at 350° C., wherein said gate electrode comprises a split-level structure comprising a middle region and outer region on at least one side of said middle region, such that said contact portion of said middle region is contacting said barrier layer and said contact portion of said outer regions is contacting said spacer layer.
2. The transistor device of claim 1 , wherein said semiconductor layers comprise gallium nitride (GaN) based layers.
3. The transistor device of claim 1 , wherein said contact portion comprises a nickel-chromium alloy (NiCr).
4. The transistor device of claim 3 , wherein said NiCr alloy comprises more than zero percent (0%) chromium and not more than ninety percent (90%) chromium.
5. The transistor device of claim 3 , wherein said NiCr alloy comprises approximately eighty percent (80%) nickel by weight and approximately twenty percent (20%) chromium by weight.
6. The transistor device of claim 3 , wherein said NiCr alloy comprises approximately fifty percent (50%) nickel by weight and approximately fifty percent (50%) chromium by weight.
7. The transistor device of claim 1 , wherein said contact portion comprises polycrystalline indium nitride (InN).
8. The transistor device of claim 1 , wherein said contact portion comprises a thickness of not less than 5 nm and not more than 100 nm.
9. The transistor device of claim 1 , wherein said contact portion comprises a thickness of approximately 20 nm.
10. A transistor device, comprising:
a plurality of semiconductor layers;
a gate electrode on said semiconductor layers, said gate electrode comprising:
a contact portion contacting said semiconductor layers, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4 eV and an RF output power degradation of not more than 0.5 dB after 100 hours of operation at 350° C.;
a diffusion barrier on said contact portion, such that said contact portion is between said diffusion barrier and said semiconductor layers;
a lateral conduction layer on said diffusion barrier; and
a protective layer on said lateral conduction layer.
11. The transistor device of claim 10 , wherein said diffusion barrier comprises a thickness of not less than 10 nm and not more than 100 nm.
12. The transistor device of claim 10 , wherein said diffusion barrier comprises a thickness of approximately 30 nm.
13. The transistor device of claim 10 , wherein said lateral conduction layer comprises gold (Au).
14. The transistor device of claim 10 , wherein said protective layer comprises nickel (Ni).
15. The transistor device of claim 10 , wherein said lateral conduction layer comprises a thickness of not less than 100 nm and not more than 2000 nm.
16. The transistor device of claim 10 , wherein said lateral conduction layer comprises a thickness of approximately 400 nm.
17. The transistor device of claim 10 , wherein said protective layer comprises a thickness of not less than 10 nm and not more than 100 nm.
18. The transistor device of claim 10 , wherein said protective layer comprises a thickness of approximately 30 nm.
19. A gate electrode for use in a transistor device, comprising:
a contact portion, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4 eV and an RF output power degradation of not more than 0.5 dB after 100 hours of operation at 350° C.;
a diffusion barrier on said contact portion;
a lateral conduction layer on said diffusion barrier; and
a protective layer on said lateral conduction layer, wherein said protective layer is resistant to one or more treatment processes including ion bombardment.
20. A gate electrode for use in a semiconductor device, comprising:
a contact portion, said contact portion comprising nickel chromium (NiCr);
a diffusion barrier on said contact portion;
a lateral conduction layer on said diffusion barrier; and
a protective layer on said lateral conduction layer, wherein said protective layer is configured to shield said lateral conduction layer from one or more processes including a corrosive process.
21. The gate electrode of claim 20 , wherein said diffusion barrier comprises platinum (Pt), said lateral conduction barrier comprises gold (Au), and said protective layer comprises nickel (Ni).