Semiconductor devices having gate resistors with low variation in resistance values
Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.
1. A semiconductor device, comprising:
a semiconductor layer structure; and
a gate structure that comprises a lumped gate resistor on an upper side of the semiconductor layer structure;
wherein a horizontal cross-section of the lumped gate resistor defines a closed shape that does not have sharp corners.
2. The semiconductor device of claim 1 , wherein the closed shape is an elliptical ring.
3. The semiconductor device of claim 1 , wherein the closed shape is a first closed shape, and wherein a dielectric pattern having a horizontal cross-section that defines a second closed shape is positioned directly above the lumped gate resistor.
4. The semiconductor device of claim 3 , wherein the dielectric pattern is a first dielectric pattern and the gate structure further comprises a second dielectric pattern and an inner contact, wherein the inner contact separates the first dielectric pattern from the second dielectric pattern.
5. The semiconductor device of claim 1 , wherein the closed shape is an annular ring.
6. The semiconductor device of claim 1 , wherein a separation between an inner edge of the closed shape and an outer edge of the closed shape is a variable distance.
7. The semiconductor device of claim 1 , wherein the closed shape is a partial ring that extends to a periphery of the semiconductor device.
8. The semiconductor device of claim 7 , wherein the partial ring has an annular semicircular horizontal cross-section or a quarter circle horizontal cross-section.
9. A semiconductor device, comprising:
a semiconductor layer structure; and
a gate structure on the semiconductor layer structure, the gate structure comprising an inner contact, an outer contact and a lumped gate resistor comprising a first material,
wherein at least one of the inner contact and the outer contact has a curved sidewall that is substantially aligned with a sidewall of the lumped gate resistor,
wherein a resistance value of the lumped gate resistor is a function of a sheet resistance of the first material layer and a separation between the inner contact and the outer contact.
10. The semiconductor device of claim 9 , wherein both an outer edge of the inner contact and an inner edge of outer contact have curved sidewalls.
11. The semiconductor device of claim 10 , wherein a separation between the outer edge of the inner contact and the inner edge of the outer contact varies along the length of the lumped gate resistor.
12. The semiconductor device of claim 9 , wherein at least a portion of the lumped gate resistor has a horizontal cross-section that defines at least a portion of an elliptical ring.
13. The semiconductor device of claim 9 , wherein a horizontal cross-section of the lumped gate resistor defines a semi-elliptical ring, and the lumped gate resistor is positioned adjacent an edge of the semiconductor device.
14. The semiconductor device of claim 9 , wherein a horizontal cross-section of the lumped gate resistor defines approximately one-quarter of an elliptical ring and the lumped gate resistor is positioned adjacent a corner of the semiconductor device.
15. A semiconductor device, comprising:
a semiconductor layer structure; and
a gate structure on an upper side of the semiconductor layer structure, the gate structure comprising a dielectric pattern that has a curved inner sidewall and a curved outer sidewall.
16. The semiconductor device of claim 15 , wherein the gate structure further comprises a lumped gate resistor that is directly underneath the dielectric pattern.
17. The semiconductor device of claim 16 , wherein the lumped gate resistor is a portion of a semiconductor layer that is directly underneath the dielectric pattern, and wherein first and second opposed sidewalls of the lumped gate resistor are substantially aligned with first and second opposed sidewalls of the dielectric pattern.
18. The semiconductor device of claim 17 , wherein the gate structure further comprises a gate pad, one or more gate buses and a plurality of gate fingers, and wherein the lumped gate resistor is interposed electrically between the gate pad and the one or more gate buses.
19. The semiconductor device of claim 18 , wherein the gate pad and the one or more gate buses each comprise a metal.
20. The semiconductor device of claim 16 , wherein the lumped gate resistor is on top of a field oxide layer.
21. The semiconductor device of claim 18 , wherein at least a portion of the dielectric pattern is underneath the gate pad.