Dielectric solder barrier for semiconductor devices
View Patent ↗The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from a second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers, and a second metallization layer on the second surface of the substrate and within the via. A portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers. The semiconductor die further includes a dielectric solder barrier on the second metallization layer. Preferably, the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via.
1. A semiconductor die comprising:
a substrate having a first surface and a second surface;
a semiconductor body on the first surface of the substrate;
one or more first metallization layers on the semiconductor body opposite the substrate;
a via that extends from the second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers;
a second metallization layer on the second surface of the substrate and within the via such that a portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers; and
a dielectric solder barrier on the second metallization layer.
2. The semiconductor die of claim 1 wherein the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via.
3. The semiconductor die of claim 2 wherein the dielectric solder barrier is on the surface of the second metallization layer opposite side-walls and a terminating end of the via and extends laterally on the surface of the second metallization layer around a periphery of the via.
4. The semiconductor die of claim 3 wherein the dielectric solder barrier extends laterally on the surface of the second metallization layer around the periphery of the via such that the dielectric solder barrier is on only a portion of the second metallization layer opposite the second surface of the substrate.
5. The semiconductor die of claim 3 wherein the dielectric solder barrier prevents solder from coming into contact with the portion of the second metallization layer within the via when the semiconductor die is attached to a mounting substrate.
6. The semiconductor die of claim 3 wherein the dielectric solder barrier layer comprises at least one of a group consisting of: one or more Plasma Enhanced Chemical Vapor Deposited dielectric layers and one or more Atomic Layer Deposited dielectric layers.
7. The semiconductor die of claim 3 wherein the dielectric solder barrier comprises one or more oxide layers.
8. The semiconductor die of claim 7 wherein the one or more oxide layers comprise at least one of a group consisting of: one or more Plasma Enhanced Chemical Vapor Deposited oxide layers and one or more Atomic Layer Deposited oxide layers.
9. The semiconductor die of claim 3 wherein the dielectric solder barrier comprises a Silicon Dioxide layer.
10. The semiconductor die of claim 9 wherein the Silicon Dioxide layer is a Plasma Enhanced Chemical Vapor Deposited Silicon Dioxide layer.
11. The semiconductor die of claim 3 wherein the dielectric solder barrier comprises an Aluminum Oxide layer.
12. The semiconductor die of claim 11 wherein the Aluminum Oxide layer is an Atomic Layer Deposited Aluminum Oxide layer, and the dielectric solder barrier further comprises a Silicon Dioxide layer on a surface of the Atomic Layer Deposited Aluminum Oxide layer opposite the second metallization layer.
13. The semiconductor die of claim 12 wherein the Silicon Dioxide layer is a Plasma Enhanced Chemical Vapor Deposited Silicon Dioxide layer.
14. The semiconductor die of claim 3 wherein the dielectric solder barrier comprises one or more of a group consisting of: an Aluminum Oxide layer, a Silicon Dioxide layer, a Silicon Nitride layer, a Hafnium Oxide layer, and a Titanium Oxide layer.
15. The semiconductor die of claim 3 wherein the dielectric solder barrier is non-wetting with respect to Tin.
16. A method comprising:
providing a semiconductor die comprising a substrate having a first surface and a second surface, a semiconductor body on the first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, and a via that extends from the second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers;
depositing a second metallization layer on the second surface of the substrate and within the via such that a portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers; and
forming a dielectric solder barrier on the second metallization layer.
17. The method of claim 16 wherein forming the dielectric solder barrier layer comprises forming the dielectric solder barrier layer on a surface of the portion of the second metallization layer within the via.
18. The method of claim 17 wherein forming the dielectric solder barrier comprises forming the dielectric solder barrier such that the dielectric solder barrier is on the surface of the second metallization layer opposite side-walls and a terminating end of the via and extends laterally on the surface of the second metallization layer around a periphery of the via.
19. The method of claim 18 wherein forming the dielectric solder barrier further comprises forming the dielectric solder barrier such that the dielectric solder barrier extends laterally on the surface of the second metallization layer around the periphery of the via such that the dielectric solder barrier is on only a portion of the second metallization layer opposite the second surface of the substrate.
20. The method of claim 18 wherein the dielectric solder barrier prevents solder from coming into contact with the portion of the second metallization layer within the via when the semiconductor die is attached to a mounting substrate.
21. The semiconductor die of claim 18 wherein the dielectric solder barrier comprises one or more layers selected from a group consisting of: an Aluminum Oxide layer, a Silicon Dioxide layer, a Silicon Nitride layer, a Hafnium Oxide layer, and a Titanium Oxide layer.
22. The method of claim 21 wherein forming the dielectric solder barrier comprises depositing the one or more layers using at least one of a group consisting of: a Plasma Enhanced Chemical Vapor Deposition process and an Atomic Layer Deposition process.
23. The method of claim 18 wherein the dielectric solder barrier is non-wetting with respect to Tin.